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AD823A-2ARM-EBZ PDF预览

AD823A-2ARM-EBZ

更新时间: 2022-10-09 09:18:41
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
20页 509K
描述
Wide Supply Dual, 17 MHz, Rail-to-Rail

AD823A-2ARM-EBZ 数据手册

 浏览型号AD823A-2ARM-EBZ的Datasheet PDF文件第14页浏览型号AD823A-2ARM-EBZ的Datasheet PDF文件第15页浏览型号AD823A-2ARM-EBZ的Datasheet PDF文件第16页浏览型号AD823A-2ARM-EBZ的Datasheet PDF文件第17页浏览型号AD823A-2ARM-EBZ的Datasheet PDF文件第18页浏览型号AD823A-2ARM-EBZ的Datasheet PDF文件第20页 
Data Sheet  
AD823A  
MAXIMIZING PERFORMANCE THROUGH PROPER  
LAYOUT  
V
V
OUT  
OUT  
V
IN  
V
To achieve the maximum performance of the extremely high  
input impedance and low offset voltage of the AD823A, care  
should be taken in the circuit board layout. The PCB surface  
must remain clean and free of moisture to avoid leakage currents  
between adjacent traces. Surface coating of the circuit board  
reduces surface moisture and provides a humidity barrier, reducing  
parasitic resistance on the board. The use of guard rings around the  
amplifier inputs further reduces leakage currents. Figure 48 shows  
how the guard rings should be configured, and Figure 49 shows  
the top view of how a surface-mount layout can be arranged. The  
guard ring does not need to be a specific width, but it should form  
a continuous loop around both inputs. By setting the guard ring  
voltage equal to the voltage at the non-inverting input, parasitic  
capacitance is minimized as well. For further reduction of leakage  
currents, components can be mounted to the PCB using Teflon®  
standoff insulators.  
IN  
AD823A  
AD823A  
V
IN  
V
OUT  
AD823A  
Figure 48. Guard Ring Layout and Connections to  
Reduce PCB Leakage Currents  
V+  
R1  
R2  
AD823A  
R2  
R1  
V
IN1  
V
IN2  
GUARD  
RING  
GUARD  
RING  
V
REF  
V
REF  
V–  
Figure 49. Top View of AD823A SOIC Layout with Guard Rings  
Rev.B | Page 19 of 20  
 
 
 

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