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AD8229

更新时间： 2024-01-08 20:33:19
品牌 Logo 应用领域
亚德诺 - ADI 仪表放大器
页数 文件大小 规格书
24页 825K
描述
1nV/√Hz Low Noise 210°C Instrumentation Amplifier

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AD8229 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：DIP
包装说明：ROHS COMPLIANT, SIDE BRAZED, CERAMIC, DIP-8针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.31.00.01风险等级：2.33
Samacsys Confidence：Samacsys Status：Released
Schematic Symbol：https://componentsearchengine.com/symbol.php?partID=420417PCB Footprint：https://componentsearchengine.com/footprint.php?partID=420417
Samacsys PartID：420417Samacsys Image：https://componentsearchengine.com/Images/9/AD8229HDZ.jpg
Samacsys Thumbnail Image：https://componentsearchengine.com/Thumbnails/1/AD8229HDZ.jpgSamacsys Pin Count：8
Samacsys Part Category：Integrated CircuitSamacsys Package Category：Other
Samacsys Footprint Name：DIP254P762X355-8PSamacsys Released Date：2017-01-10 13:33:33
Is Samacsys：N放大器类型：INSTRUMENTATION AMPLIFIER
最大平均偏置电流 (IIB)：0.07 µA标称带宽 (3dB)：15 MHz
最小共模抑制比：86 dB最大输入失调电流 (IIO)：0.035 µA
最大输入失调电压：100 µVJESD-30 代码：R-CDIP-T8
JESD-609代码：e4长度：13.208 mm
负供电电压上限：-17 V标称负供电电压 (Vsup)：-15 V
功能数量：1端子数量：8
最高工作温度：210 °C最低工作温度：-40 °C
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：DIP
封装等效代码：DIP8,.3封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：+-15 V认证状态：Not Qualified
座面最大高度：4.09 mm标称压摆率：22 V/us
子类别：Instrumentation Amplifier最大压摆率：7 mA
供电电压上限：17 V标称供电电压 (Vsup)：15 V
表面贴装：NO温度等级：AUTOMOTIVE
端子面层：GOLD端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED最大电压增益：1000
最小电压增益：1标称电压增益：10
宽度：7.62 mmBase Number Matches：1

AD8229 数据手册

 浏览型号AD8229的Datasheet PDF文件第15页浏览型号AD8229的Datasheet PDF文件第16页浏览型号AD8229的Datasheet PDF文件第17页浏览型号AD8229的Datasheet PDF文件第19页浏览型号AD8229的Datasheet PDF文件第20页浏览型号AD8229的Datasheet PDF文件第21页 
AD8229  
For best performance, source impedance to the REF terminal  
should be kept well below 1 Ω. As shown in Figure 55, the  
reference terminal, REF, is at one end of a 5 kΩ resistor.  
Additional impedance at the REF terminal adds to this 5 kΩ  
resistor and results in amplification of the signal connected to  
the positive input. The amplification from the additional RREF  
can be calculated as follows:  
Common-Mode Rejection Ratio over Frequency  
Poor layout can cause some of the common-mode signals to be  
converted to differential signals before reaching the in-amp.  
Such conversions occur when one input path has a frequency  
response that is different from the other. To keep CMRR over  
frequency high, the input source impedance and capacitance of  
each path should be closely matched. Additional source resis-  
tance in the input path (for example, for input protection)  
should be placed close to the in-amp inputs, which minimizes  
their interaction with parasitic capacitance from the PCB traces.  
2(5 kΩ + RREF)/(10 kΩ + RREF  
)
Only the positive signal path is amplified; the negative path  
is unaffected. This uneven amplification degrades CMRR.  
Parasitic capacitance at the gain setting pins can also affect CMRR  
over frequency. If the board design has a component at the gain  
setting pins (for example, a switch or jumper), the component  
should be chosen so that the parasitic capacitance is as small as  
possible.  
INCORRECT  
CORRECT  
AD8229  
AD8229  
REF  
REF  
V
V
Power Supplies  
+
A stable dc voltage should be used to power the instrumentation  
amplifier. Noise on the supply pins can adversely affect perfor-  
mance. See the PSRR performance curves in Figure 19 and  
Figure 20 for more information.  
OP1177  
–
Figure 56. Driving the Reference Pin  
A 0.1 µF capacitor should be placed as close as possible to each  
supply pin. As shown in Figure 58, a 10 µF tantalum capacitor  
can be used farther away from the part. In most cases, it can be  
shared by other precision integrated circuits.  
INPUT VOLTAGE RANGE  
Figure 10 through Figure 15 show the allowable common-mode  
input voltage ranges for various output voltages and supply  
voltages. The 3-op-amp architecture of the AD8229 applies gain  
in the first stage before removing common-mode voltage with  
the difference amplifier stage. Internal nodes between the first and  
second stages (Node 1 and Node 2 in Figure 55) experience a  
combination of a gained signal, a common-mode signal, and a  
diode drop. This combined signal can be limited by the voltage  
supplies even when the individual input and output signals are  
not limited.  
+V  
S
0.1µF  
10µF  
+IN  
–IN  
V
OUT  
R
G
AD8229  
LOAD  
REF  
LAYOUT  
To ensure optimum performance of the AD8229 at the PCB  
level, care must be taken in the design of the board layout. The  
pins of the AD8229 are arranged in a logical manner to aid in  
this task.  
0.1µF  
10µF  
–V  
S
Figure 58. Supply Decoupling, REF, and Output Referred to Local Ground  
Reference Pin  
1
2
3
4
8
7
6
5
+V  
V
–IN  
S
The output voltage of the AD8229 is developed with respect to  
the potential on the reference terminal. Care should be taken to  
tie REF to the appropriate local ground.  
R
G
OUT  
R
REF  
–V  
G
+IN  
S
AD8229  
TOP VIEW  
(Not to Scale)  
Figure 57. Pinout Diagram  
Rev. 0 | Page 18 of 24  
 
 
 
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