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AD8205YR

更新时间： 2024-02-08 19:37:35
品牌 Logo 应用领域
亚德诺 - ADI 运算放大器放大器电路光电二极管
页数 文件大小 规格书
12页 308K
描述
Single-Supply 42 V System Difference Amplifier

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AD8205YR 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP, SOP8,.25针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.31.00.01风险等级：0.68
放大器类型：OPERATIONAL AMPLIFIER标称共模抑制比：80 dB
最大输入失调电压：4500 µVJESD-30 代码：R-PDSO-G8
JESD-609代码：e3长度：4.9 mm
湿度敏感等级：1功能数量：1
端子数量：8最高工作温度：125 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP8,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260电源：5 V
认证状态：Not Qualified座面最大高度：1.75 mm
子类别：Operational Amplifier最大压摆率：2 mA
供电电压上限：12.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES温度等级：AUTOMOTIVE
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：3.9 mm
Base Number Matches：1

AD8205YR 数据手册

 浏览型号AD8205YR的Datasheet PDF文件第5页浏览型号AD8205YR的Datasheet PDF文件第6页浏览型号AD8205YR的Datasheet PDF文件第7页浏览型号AD8205YR的Datasheet PDF文件第9页浏览型号AD8205YR的Datasheet PDF文件第10页浏览型号AD8205YR的Datasheet PDF文件第11页 
AD8205  
THEORY OF OPERATION  
The AD8205 is a single-supply difference amplifier that uses a  
unique architecture to accurately amplify small differential cur-  
rent shunt voltages in the presence of rapidly changing common-  
mode voltages. It is offered in both packaged and die form.  
By attenuating the voltages at Pin 1 and Pin 8, the A1 amplifier  
inputs are held within the power supply range, even if Pin 1 and  
Pin 8 exceed the supply or fall below common (ground). A ref-  
erence voltage of 250 mV biases the attenuator above ground.  
This allows the amplifier to operate in the presence of negative  
common-mode voltages.  
In typical applications, the AD8205 is used to measure current  
by amplifying the voltage across a current shunt placed across  
the inputs.  
The input network also attenuates normal (differential) mode  
voltages. A1 amplifies the attenuated signal by 26. The input and  
output of this amplifier are differential to maximize the ac  
common-mode rejection.  
The gain of the AD8205 is 50 V/V, with an accuracy of 1.2%.  
This accuracy is guaranteed over the operating temperature  
range of −40°C to +125°C. The die temperature range is −40°C  
to +150°C with a guaranteed gain accuracy of 1.3%.  
A2 converts the differential voltage from A1 into a single-ended  
signal and provides further amplification. The gain of this sec-  
ond stage is 32.15.  
The input offset is less than 2 mV referred to the input at 25°C,  
and 4.5 mV maximum referred to the input over the full operat-  
ing temperature range for the packaged part. The die input off-  
set is less than 6 mV referred to the input over the die operating  
temperature range.  
The reference inputs, VREF1 and VREF2, are tied through resistors  
to the positive input of A2, which allows the output offset to be  
adjusted anywhere in the output operating range. The gain is  
1 V/V from the reference pins to the output when the reference  
pins are used in parallel. The gain is 0.5 V/V when they are used  
to divide the supply.  
The AD8205 operates with a single supply from 4.5 V to 10 V (ab-  
solute maximum = 12.5 V). The supply current is less than 2 mA.  
High accuracy trimming of the internal resistors allows the  
AD8205 to have a common-mode rejection ratio better than  
78 dB from dc to 20 kHz. The common-mode rejection ratio  
over the operating temperature is 76 dB for both the die and  
packaged part.  
The ratios of Resistors RA, RB, RC, RD, and RF are trimmed to a  
high level of precision to allow the common-mode rejection  
ratio to exceed 80 dB. This is accomplished by laser trimming  
the resistor ratio matching to better than 0.01%.  
The total gain of 50 is made up of the input attenuation of  
1/16.7 multiplied by the first stage gain of 26 and the second  
stage gain of 32.15.  
The output offset can be adjusted from 0.05 V to 4.8 V (V+ =  
5 V) for unipolar and bipolar operation.  
The AD8205 consists of two amplifiers (A1 and A2), a resistor  
network, small voltage reference, and a bias circuit (not shown),  
see Figure 13.  
The output stage is Class A with a PNP pull-up transistor and a  
300 µA current sink pull-down.  
–IN  
+IN  
The set of input attenuators preceding A1 consist of RA, RB, and  
RC, which reduce the common-mode voltage to match the input  
voltage range of A1. The two attenuators form a balanced bridge  
network. When the bridge is balanced, the differential voltage  
created by a common-mode voltage is 0 V at the inputs of A1.  
The input attenuation ratio is 1/16.7. The combined series resis-  
tance of RA, RB, and RC is approximately 200 kΩ 20%.  
R
R
A
A
A1  
R
R
R
R
R
R
R
R
D
B
B
F
F
D
V
V
A2  
OUT  
C
C
1
REF  
R
R
F
E
AD8205  
R
R
250mV  
GND  
REF  
REF  
V
2
REF  
Figure 13. Simplified Schematic  
Rev. 0 | Page 8 of 12  
 
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