Datasheet > AD8156-EVALZ

AD8156-EVALZ

更新时间： 2024-02-18 02:37:39

品牌	Logo	应用领域
亚德诺 - ADI		开关
页数	文件大小	规格书
20页	527K
描述
6.25 Gbps 4】4 Digital Crosspoint Switch with EQ

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技术参数
数据手册

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AD8156-EVALZ 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	8 X 8 MM, 1 MM PITCH, ROHS COMPLIANT, MO-192ABB-1, BGA-49	针数：	49
Reach Compliance Code：	unknown	ECCN代码：	5A991.B.1
HTS代码：	8542.39.00.01	风险等级：	8.37
模拟集成电路 - 其他类型：	CROSS POINT SWITCH	JESD-30 代码：	S-PBGA-B49
JESD-609代码：	e1	长度：	8 mm
湿度敏感等级：	3	信道数量：	4
功能数量：	1	端子数量：	49
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装形状：	SQUARE	封装形式：	GRID ARRAY
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	1.85 mm	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	40	宽度：	8 mm

AD8156-EVALZ 数据手册

AD8156

ADDRESS PINS, A[3:0] INPUTS

DATA PINS, D[3:0] INPUTS/OUTPUTS

The AD8156 feature sets can be set port by port or globally.

A[3:2] specify what is being programmed or read back when

the part is being configured port by port. Connectivity, output

current, equalization, or global programming features are

chosen based on the values of A[3:2]. Similarly, A[1:0] address

the port that is being programmed or read back. In global

programming, A[1:0] serve a different function. Refer to Table 9

to Table 15 for programming examples.

In readback mode, the D[3:0] pins are low impedance outputs

indicating the stored values in the memory to be read. The

readback drivers are designed to drive high impedances only,

so external drivers connected to D[3:0] must be disabled during

readback mode.

CONTROL INTERFACE LEVELS

The AD8156 control interface shares the data path supply pins,

V_CCand V_EE. The potential between the positive logic supply

V_CCand the negative supply V_EEmust be at least 3.0 V and no

more than 3.7 V. Regardless of supply, the logic threshold is

approximately one-half the supply range, allowing the interface

to be used with most LVCMOS- and LVTTL-logic drivers.

Table 7. Dual 2 × 2 Mode Programming Table

Address A[3:0]

Data D[3:0]

Input A3 to Input A0 enable Output 3 to Output 0, respectively. Input D3 to Input D0 control the connectivity of Output 3 to Output 0, respectively.

1 = Enables the output (for all A[3:0] inputs)

0 = Disables the output (for all A[3:0] inputs)

0 = Input 2, 1 = Input 3 (for D2 and D3)

0 = Input 0, 1 = Input 1 (for D0 and D1)

Table 8. 4 × 4 Mode Programming Table

Mode

Address A[3:0]

Data D[3:0]

Write/Read Connectivity

and Disable

0 0 A1 A0

A1 and A0 determine which

output is being programmed.

0 D2 D1 D0

D1 and D0 determine which input is connected to which output;

D2 determines the enabled/disabled state of that output, with D2 = 1

(enable). When writing or reading, D3 is always 0.

Write/Read Output

Current Level

0 1 A1 A0

A1 and A0 determine which

output is being programmed.

D3 D2 D1 D0

D0 to D3 binarily program the output current level/voltage swing with the

output current = 2 mA + (2 mA × decimal (D[3:0])).

Broadcast

1 0 0 0

0 D2 D1 D0

Connectivity/Disable

D1 and D0 determine which input is connected to all of the outputs.

D2 determines the enabled/disabled state of all outputs with D2 = 1 (enable).

When writing or reading, D3 is always 0.

Broadcast Output

Current Level

1 0 0 1

D3 D2 D1 D0

D0 to D3 binarily program the output current level/voltage swing with the

output current = 2 mA + (2 mA × decimal (D[3:0])). The value is written to

all outputs.

Broadcast EQ Setting

Program EQ Setting

1 0 1 1

D3 D2 D1 D0

Data inputs D0 to D3 set the input equalization level where:

Gain(f) = D[3:0]/15 × 40 log₁₀(f/0.83 GHz).

1 1 A1 A0

D3 D2 D1 D0

A1 and A0 determine which

input is being programmed.

D0 to D3 set the input equalization level, where:

Gain(f) = D[3:0]⁄15 × 40 log₁₀(f⁄0.83 GHz).

Rev. 0 | Page 16 of 20

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