AD8156
CONTROL INTERFACE DESCRIPTION
The control interface for the AD8156 consists of a set of
address, data, and several control pins. All control pins are
active low. The control interface is level sensitive.
RST
all outputs are connected but disabled.
other control pins.
overrides all of the
Pin
CS
CONTROL PINS
The chip select pin, an active low signal, facilitates multiple chip
address decoding. All control signals, except the reset signal, are
All control pins on the chip are level-sensitive, not edge-triggered.
The preferred programming method is to assert the data and
address pins to their desired configuration, wait one control bit
CS
ignored when is pulled high. The pin disables the control signals
CS
and does not affect operation of the chip. does not power down
WE
period, then pull
low to write to the first bank of registers.
WE
any of the latches, preserving any data programmed in the latches.
After one control bit period,
is pulled high. After an
MODE Pin
additional control bit period, the address and data pins can be
set to their next values, and the cycle repeats. Using this
method, each write takes three control bit periods.
The MODE pin sets the part in 4 × 4 mode or dual 2 × 2 mode.
Pulling MODE low sets the part in 4 × 4 mode, and pulling
MODE high sets the part in dual 2 × 2 mode. In dual 2 × 2
UPD
After the first bank of registers is programmed,
which transfers the data from the first bank of latches to the second
UPD
is pulled low,
WE RE
UPD
mode, the
,
, and
pins are unused.
Pin
WE
This pin is the write enable to the first bank of registers. Forcing
WE
bank of latches. When
regardless of the status of the address, data,
UPD
is pulled low, the full chip updates,
WE RE
, or
pins.
to logic low allows the data on the D[3:0] pins to be stored
in the first bank of latches for the function specified by A[3:0].
WE
Writing to the part while
is pulled low writes through the
first bank of registers and into the second bank, immediately
affecting the connectivity and output current of the part. It is
recommended that the user write to the first bank with one data
The
pin must be returned to logic high state before
changing the other pins after a write cycle to avoid overwriting
the first bank data.
UPD
bit cycle, and subsequently activate the
pin low, because
Pin
UPD
This pin is the write enable to the second bank of registers.
UPD
data and address pin skews presented to the part can lead to
errors when writing through both banks simultaneously. If
skews are properly controlled, a transparent write can allow a
very quick change of states in 4 × 4 mode.
Forcing
to logic low transfers the data stored in all first
bank latches to the second bank latches, which is the active set
of registers. The chip functions update during this operation.
Pin
RST
RST
Pin
At any time, a reset pulse to
can be applied to the control
RE
This pin is the read enable for the second bank of registers.
RE
interface to globally reset all first and second bank latches to
their default values. The device has an internal power-on reset
circuit, but it is recommended that
power-up. The default values for the chip include disabling all
outputs, turning off equalization, and setting output current code to
the default, b0111 (16 mA). The default connection is the buffer
state, or IN0 → OUT0, IN1 → OUT1, IN2 → OUT2, IN3 → OUT3;
Forcing
to logic low enables the on-chip drivers to drive the
RST
be held low during
bidirectional D[3:0] pins. The on-chip drivers are only intended
to drive high impedance loads, so any external drivers of D[3:0]
must be disabled when
RE
is low.
Table 6. Basic Control Pin Functions
RST CS MODE WE RE UPD Function
1
1
x
x
x
x
Control Interface Disabled. Prior settings are stored, and the chip is run based on the
configuration data stored (in 4 × 4 mode) or set (in dual 2 × 2 mode) previously.
0
1
x
0
x
0
x
1
x
1
x
1
Global Reset. Disables all outputs and equalizers. Output current code set to 0111 (16 mA).
4 × 4 Mode. Address and data pins are ignored (values in the AD8156 memory control connectivity,
output current, and EQ setting).
1
1
1
0
0
0
0
0
0
0
1
1
1
0
x
1
1
0
Write Enable. Writes to the first bank of registers.
Readback Enable. Reads back data on D[3:0] from the addressed latch (second bank of registers).
Global Update. Transfers data from first bank of registers to second bank of registers (active set).
Chip functions update.
1
1
0
0
0
1
0
x
x
x
0
x
Transparent Write. Writes and updates simultaneously through first bank to the second bank of
registers. Chip functions update.
Dual 2 × 2 Mode. Address and data pins asynchronously control the device.
Rev. 0 | Page 15 of 20
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