Datasheet > AD8138_06

AD8138_06

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
亚德诺 - ADI		驱动器
页数	文件大小	规格书
24页	451K
描述
Low Distortion Differential ADC Driver

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AD8138_06 数据手册

AD8138

HIGH PERFORMANCE ADC DRIVING

The circuit in Figure 46 shows a simplified front-end

connection for an AD8138 driving an AD9224, a 12-bit,

40 MSPS ADC. The ADC works best when driven differentially,

which minimizes its distortion. The AD8138 eliminates the

need for a transformer to drive the ADC and performs single-

ended-to-differential conversion, common-mode level-shifting,

and buffering of the driving signal.

The signal generator has a ground-referenced, bipolar output,

that is, it drives symmetrically above and below ground.

Connecting V_OCMto the CML pin of the AD9224 sets the output

common-mode of the AD8138 at 2.5 V, which is the midsupply

level for the AD9224. This voltage is bypassed by a 0.1 μF

capacitor.

The full-scale analog input range of the AD9224 is set to

4 V p-p, by shorting the SENSE terminal to AVSS. This has

been determined to be the scaling to provide minimum

harmonic distortion.

The positive and negative outputs of the AD8138 are connected

to the respective differential inputs of the AD9224 via a pair of

49.9 Ω resistors to minimize the effects of the switched-capacitor

front end of the AD9224. For best distortion performance, it

runs from supplies of 5 V.

For the AD8138 to swing at 4 V p-p, each output swings 2 V p-p

while providing signals that are 180° out of phase. With a

common-mode voltage at the output of 2.5 V, each AD8138

output swings between 1.5 V and 3.5 V.

The AD8138 is configured with unity gain for a single-ended,

input-to-differential output. The additional 23 Ω, 523 Ω total, at

the input to −IN is to balance the parallel impedance of the

50 Ω source and its 50 Ω termination that drives the

noninverting input.

A ground-referenced 4 V p-p, 5 MHz signal at D_IN+ was used to

test the circuit in Figure 46. When the combined-device circuit

was run with a sampling rate of 20 MSPS, the spurious-free

dynamic range (SFDR) was measured at −85 dBc.

+5V

0.1pF

499Ω

15 26

49.9Ω

499Ω

AVDD DRVDD

AD9224

VINB

DIGITAL

OUTPUTS

OCM

50Ω

SOURCE

49.9Ω

AD8138

523Ω

VINA

AVSS SENSE CML DRVSS

16 25

0.1pF

499Ω

–5V

Figure 46. AD8138 Driving an AD9224, a 12-Bit, 40 MSPS ADC

Rev. F | Page 21 of 24

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