Datasheet > AD8108_15

AD8108_15

更新时间： 2022-02-26 12:59:49

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
33页	1020K
描述
325 MHz, 8 8 Buffered Video Crosspoint Switches

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AD8108_15 数据手册

AD8108/AD8109

TIMING CHARACTERISTICS (PARALLEL)

Table 4. Timing Characteristics

Parameter

Symbol

Min

100

Typ

Max

Unit

Data Setup Time

CLK Pulse Width

Data Hold Time

CLK Pulse Separation

CLK to UPDATE Delay

UPDATE Pulse Width

Propagation Delay, UPDATE to Switch On or Off

CLK, UPDATE Rise and Fall Times

RESET Time

t₁

t₂

t₃

t₄

t₅

t₆

–

100

–

200

Table 5. Logic Levels

V_IH

V_IL

V_OH

V_OL

I_IH

I_IL

I_OH

I_OL

RESET, SER/PAR

CLK, D0, D1, D2,

D3, A0, A1, A2

CE, UPDATE

RESET, SER/PAR

CLK, D0, D1, D2,

D3, A0, A1, A2

CE, UPDATE

DATA OUT

RESET, SER/PAR

CLK, D0, D1, D2,

D3, A0, A1, A2

CE, UPDATE

RESET SER/PAR

CLK, D0, D1, D2,

D3, A0, A1, A2

CE, UPDATE

DATA OUT

2.0 V min

0.8 V max

2.7 V min

0.5 V max

20 µA max

−400 µA min

−400 µA max

3.0 mA min

t₂

t₄

CLK

t₁

t₃

D0–D3

A0–A2

t₅

t₆

1 = LATCHED

UPDATE

0 = TRANSPARENT

Figure 3. Timing Diagram, Parallel Mode

Rev. B | Page 6 of 32

1...4 5 678 9 10...33

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