AD8074ARUZ

更新时间： 2024-02-20 06:56:37

品牌	Logo	应用领域
亚德诺 - ADI		缓冲放大器放大器电路光电二极管 PC
页数	文件大小	规格书
15页	755K
描述
500 MHz, G = 1 and 2 Triple Video Buffers with Disable

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技术参数
数据手册
替代型号

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AD8074ARUZ 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	TSSOP
包装说明：	TSSOP, TSSOP16,.25	针数：	16
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	0.76
放大器类型：	BUFFER	最大平均偏置电流 (IIB)：	9.5 µA
标称带宽 (3dB)：	600 MHz	25C 时的最大偏置电流 (IIB)：	9.5 µA
最大输入失调电压：	27000 µV	JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e3	长度：	5 mm
湿度敏感等级：	1	负供电电压上限：	-6 V
标称负供电电压 (Vsup)：	-5 V	功能数量：	3
端子数量：	16	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装等效代码：	TSSOP16,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	电源：	+-5 V
认证状态：	Not Qualified	座面最大高度：	1.2 mm
标称压摆率：	1600 V/us	子类别：	Buffer Amplifier
最大压摆率：	30 mA	供电电压上限：	6 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	4.4 mm	Base Number Matches：	1

AD8074ARUZ 数据手册

AD8074/AD8075

THEORY OF OPERATION

APPLICATIONS

Response Tuning

The AD8074 (G = +1) and AD8075 (G = +2) are triple-channel,

high-speed buffers with TTL-compatible output enable control.

Optimized for buffering RGB (red, green, blue) video sources,

the devices have high peak slew rates, maintaining their band-

width for large signals. Additionally, the buffers are compensated

for high phase margin, minimizing overshoot for good pixel

resolution. The buffers also have video specifications that are

suitable for buffering NTSC or PAL composite signals.

It has been mentioned in passing that the primary cause of over-

shoot for the AD8074 and AD8075 is the presence of large

reactive loads at the output. If the system exhibits excessive

ringing while settling, a 10 Ω–50 Ω series resistor may be used

at the output to isolate the emitter-follower output buffer from

the reactive load. If the output exhibits an overdamped response,

the system designer may add a few pF shunt capacitance at the

output to tune for a faster edge transition. A system with a small

degree of overshoot will settle faster than an overdamped system.

The buffers are organized as three independent channels, each

with an input transconductance stage and an output trans-

impedance stage. Each channel is characterized by low input

capacitance and high input impedance. The transconductance

stages, NPN differential pairs, source signal current into the folded

cascode output stages. Each output stage contains a compensat-

ing network and emitter follower output buffer. Internal voltage

feedback sets the gain, the AD8074 being configured as a unity

gain follower, and the AD8075 as a gain-of-two amplifier with a

feedback network. The architecture provides drive for a reverse-

terminated video load (150 Ω) with low differential gain and

phase error for relatively low power consumption. Careful chip

design and layout allow excellent crosstalk isolation between

channels.

2.0

= 10⍀

= 10pF

1.5

1.0

= 0⍀

= 5pF

0.5

= 20⍀

= 15pF

–0.5

–1.0

–1.5

–2.0

OUT

1k⍀

75⍀

2ns

One logic pin, OE, controls whether the three outputs are

enabled, or disabled to a high-impedance state. The high imped-

ance disable allows larger matrices to be built when busing the

outputs together. When disabled, the AD8074 and AD8075 con-

sume a fifth the power as when enabled. In the case of the

AD8075 (G = +2), a feedback isolation scheme is used so that

the impedance of the gain-of-two feedback network does not

load the output.

Figure 2. Driving Capacitive Loads

Single Supply Operation

The AD8074 and AD8075 may be operated from a single 10 V

supply. In this configuration, the AD8075’s AGND pins must

be tied near midsupply, as AGND provides the reference for the

ground buffer, to which the internal gain network is terminated.

Full power bandwidth for an undistorted sinusoid is often calcu-

lated using peak slew rate from the equation:

Logic is referenced to DGND. The buffers are disabled in single

supply operation for V_OE> V_DGND+ ~2.0 V and enabled for

_OE< V_DGND+ 0.8 V. TTL logic levels are expected. The fol-

Peak Slew Rate

Full Power Bandwidth =

lowing restrictions are placed upon the digital ground potential:

2 × π × Sinusoidal Amplitude

3.5V ≤V_AVCC–V_DGND≤ 12V

V_DGND≥ V_AVEE

Peak slew rate is not the same as average slew rate (25% to

75%) which is typically specified. For a natural response, peak

slew rate may be 2.7 times larger than average slew rate. There-

fore, calculating a full power bandwidth with a specified average

slew rate will give a pessimistic result.

The architecture of the output buffer is such that the output

voltage can swing to within ~2.3 V of either rail. For example, if

the output need swing only 2 V, then the buffers could be oper-

ated on dual 3.5 V or single 7 V supplies. It is cautioned that

saturation effects may become noticeable when the output swings

within 2.6 V of either rail. The system designer may opt to

use this characteristic to his or her advantage by using the

soft-saturation regime, (2.2 V–2.6 V from the supply rails), to

tame excessive overshoot. The designer is cautioned that a

charge storage associated time delay of several nanoseconds is

incurred when recovering from soft-saturation. This effect

results in longer settling tails.

The primary cause of overshoot in these amplifiers is the pres-

ence of large reactive loads at the output and insufficient series

isolation of the load. However, it is possible to overdrive these

amplifiers with 1 V, subnanosecond input-pulse edges. The

ensuing dynamics may give rise to subnanosecond overshoot. To

reduce these effects, an edge-rate limiting network at the input

should be considered for input transition times less than 0.5 ns.

Rev. B

–9–

1...6 7 8910 11 12...15

中文翻译

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AD8074ARUZ 替代型号

型号	品牌	替代类型	描述	数据表
AD8074ARUZ-REEL7	ADI	类似代替	500 MHz, G = 1 and 2 Triple Video Buffers with Disable
AD8074ARUZ-REEL	ADI	类似代替	500 MHz, G = 1 and 2 Triple Video Buffers with Disable
AD8074ARU	ADI	类似代替	500 MHz, G = +-1 and +2 Triple Video Buffers with Disable

与AD8074ARUZ相关器件

型号	品牌	获取价格	描述	数据表
AD8074ARUZ-REEL	ADI	获取价格	500 MHz, G = 1 and 2 Triple Video Buffers with Disable
AD8074ARUZ-REEL7	ADI	获取价格	500 MHz, G = 1 and 2 Triple Video Buffers with Disable
AD8074-EVAL	ADI	获取价格	500 MHz, G = +-1 and +2 Triple Video Buffers with Disable
AD8074Z-EVAL	ADI	获取价格	500 MHz, G = 1 and 2 Triple Video Buffers with Disable
AD8075	ADI	获取价格	500 MHz, G = +-1 and +2 Triple Video Buffers with Disable
AD8075_15	ADI	获取价格	Video Buffers with Disable
AD8075ARU	ADI	获取价格	500 MHz, G = +-1 and +2 Triple Video Buffers with Disable
AD8075ARU-REEL7	ROCHESTER	获取价格	TRIPLE BUFFER AMPLIFIER, PDSO16, PLASTIC, TSSOP-16
AD8075ARUZ	ROCHESTER	获取价格	TRIPLE BUFFER AMPLIFIER, PDSO16, ROHS COMPLIANT, PLASTIC, TSSOP-16
AD8075ARUZ	ADI	获取价格	500 MHz, G = 1 and 2 Triple Video Buffers with Disable

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