AD8021ARM

更新时间： 2024-02-08 12:43:29

品牌	Logo	应用领域
亚德诺 - ADI		放大器
页数	文件大小	规格书
20页	427K
描述
Low Noise, High Speed Amplifier for 16-Bit Systems

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AD8021ARM 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	SOP,	针数：	8
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.31.00.01	风险等级：	1.68
放大器类型：	OPERATIONAL AMPLIFIER	最大平均偏置电流 (IIB)：	10.5 µA
标称共模抑制比：	98 dB	最大输入失调电压：	1000 µV
JESD-30 代码：	R-PDSO-G8	JESD-609代码：	e3
长度：	4.9 mm	湿度敏感等级：	1
负供电电压上限：	-13.2 V	标称负供电电压 (Vsup)：	-5 V
功能数量：	1	端子数量：	8
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	1.75 mm	标称压摆率：	420 V/us
子类别：	Operational Amplifier	供电电压上限：	13.2 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	BIPOLAR	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	3.9 mm
Base Number Matches：	1

AD8021ARM 数据手册

AD8021

With the AD8021, a variety of trade-offs can be made to fine-tune

its dynamic performance. Sometimes more bandwidth or slew

rate is needed at a particular gain. Reducing the compensation

capacitance, as illustrated in TPC 3, will increase the bandwidth

and peaking due to a decrease in phase margin. On the other hand,

if more stability is needed, increasing the compensation cap will

decrease the bandwidth while increasing the phase margin.

this high impedance with a current gain of 5,000, so that the

AD8021 can maintain a high open-loop gain even when driving

heavy loads.

Two internal diode clamps across the inputs (Pins 2 and 3) protect

the input transistors from large voltages that could otherwise cause

emitter-base breakdown, which would result in degradation of

offset voltage and input bias current.

As with all high speed amplifiers, parasitic capacitance and induc-

tance around the amplifier can affect its dynamic response.

Often, the input capacitance (due to the op amp itself, as well

as the PC board) could have a significant effect. The feedback

resistance, together with the input capacitance, may contribute to

a loss of phase margin, thereby affecting the high frequency response,

as shown in TPC 10. Furthermore, a capacitor (C_F) in parallel

with the feedback resistor can compensate for this phase loss.

OUTPUT

+IN

Additionally, any resistance in series with the source will create

a pole with the input capacitance (as well as dampen high fre-

quency resonance due to package and board inductance and

capacitance), the effect of which is shown in TPC 11.

INTERNAL

1.5pF

–IN

–V

It must also be noted that increasing resistor values will increase

the overall noise of the amplifier, and that reducing the feedback

resistor value will increase the load on the output stage, thus

increasing distortion (TPC 18).

COMP

Figure 6. Simplified Schematic

Using the Disable Feature

When Pin 8 (DISABLE) is approximately 2 V or more higher than

Pin 1 (LOGIC REFERENCE), the part is enabled. When Pin 8

is brought down to within about 1.5 V of Pin 1, the part is dis-

abled. See the Specification tables for exact disable and enable

voltage levels. If the disable feature is not going to be used, Pin 8

can be tied to V_Sor a logic high source, and Pin 1 can be tied to

ground or logic low. Alternatively, if Pin 1 and Pin 8 are not

connected, the part will be in an enabled state.

PCB LAYOUT CONSIDERATIONS

As with all high speed op amps, achieving optimum performance

from the AD8021 requires careful attention to PC board layout.

Particular care must be exercised to minimize lead lengths

between the ground leads of the bypass capacitors and between

the compensation capacitor and the negative supply. Otherwise,

lead inductance can influence the frequency response and even

cause high frequency oscillations. Use of a multilayer printed

circuit board, with an internal ground plane, will reduce ground

noise and enable a compact component arrangement.

THEORY OF OPERATION

The AD8021 is fabricated on the second generation of Analog

Devices’ proprietary High Voltage eXtra-Fast Complementary

Bipolar (XFCB) process, which enables the construction of PNP

and NPN transistors with similar f_Ts in the 3 GHz region. The

transistors are dielectrically isolated from the substrate (and each

other), eliminating the parasitic and latch-up problems caused

by junction isolation. It also reduces nonlinear capacitance

(a source of distortion) and allows a higher transistor f_Tfor a

given quiescent current. The supply current is trimmed, which

results in less part-to-part variation of bandwidth, slew rate,

distortion, and settling time.

Due to the relatively high impedance of Pin 5 and low values of

the compensation capacitor, a guard ring is recommended. The

guard ring is simply a PC trace that encircles Pin 5 and is

connected to the output, Pin 6, which is at the same potential as

Pin 5. This serves two functions. It shields Pin 5 from any local

circuit noise generated by surrounding circuitry. It also mini-

mizes stray capacitance, which would tend to otherwise reduce

the bandwidth. An example of a guard ring layout may be seen

in Figure 7.

Also shown in Figure 7, the compensation capacitor is located

immediately adjacent to the edge of the AD8021 package, spanning

Pin 4 and Pin 5. This capacitor must be a high quality surface-

mount COG or NPO ceramic. The use of leaded capacitors is not

recommended. The high frequency bypass capacitor(s) should

be located immediately adjacent to the supplies, Pins 4 and 7.

As shown in Figure 6, the AD8021 input stage consists of an NPN

differential pair in which each transistor operates at 0.8 mA collec-

tor current. This allows the input devices a high transconductance;

thus, the AD8021 has a low input noise of 2.1 nV/√Hz @ 50 kHz.

The input stage drives a folded cascode that consists of a pair of

PNP transistors. The folded cascode and current mirror provide

a differential to single-ended conversion of signal current. This

current then drives the high impedance node (Pin 5), where the

C_Cexternal capacitor is connected. The output stage preserves

To achieve the shortest possible lead length at the inverting

input, the feedback resistor R_Fis located beneath the board and

just spans the distance from the output, Pin 6, to inverting input

Pin 2. The return node of resistor R_Gshould be situated as

closely as possible to the return node of the negative supply

bypass capacitor connected to Pin 4.

REV. D

–16–

1...13 14 151617 18 19 20

中文翻译

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AD8021ARM 替代型号

型号	品牌	替代类型	描述	数据表
AD8021ARMZ-REEL7	ADI	类似代替	Low Noise, High Speed Amplifier for 16-Bit Systems
AD8021ARMZ-REEL	ADI	类似代替	Low Noise, High Speed Amplifier for 16-Bit Systems
AD8021ARMZ	ADI	类似代替	Low Noise, High Speed Amplifier for 16-Bit Systems

与AD8021ARM相关器件

型号	品牌	获取价格	描述	数据表
AD8021ARM-REEL	ADI	获取价格	Low Noise, High Speed Amplifier for 16-Bit Systems
AD8021ARM-REEL7	ADI	获取价格	Low Noise, High Speed Amplifier for 16-Bit Systems
AD8021ARMZ	ADI	获取价格	Low Noise, High Speed Amplifier for 16-Bit Systems
AD8021ARMZ-REEL	ADI	获取价格	Low Noise, High Speed Amplifier for 16-Bit Systems
AD8021ARMZ-REEL7	ADI	获取价格	Low Noise, High Speed Amplifier for 16-Bit Systems
AD8021AR-REEL	ADI	获取价格	Low Noise, High Speed Amplifier for 16-Bit Systems
AD8021AR-REEL7	ADI	获取价格	Low Noise, High Speed Amplifier for 16-Bit Systems
AD8021ARZ	ADI	获取价格	Low Noise, High Speed Amplifier for 16-Bit Systems
AD8021ARZ-REEL	ADI	获取价格	Low Noise, High Speed Amplifier for 16-Bit Systems
AD8021ARZ-REEL7	ADI	获取价格	Low Noise, High Speed Amplifier for 16-Bit Systems

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