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AD8013AN

更新时间： 2024-01-29 22:50:38
品牌 Logo 应用领域
亚德诺 - ADI 视频放大器
页数 文件大小 规格书
12页 321K
描述
Single Supply, Low Power, Triple Video Amplifier

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AD8013AN 数据手册

 浏览型号AD8013AN的Datasheet PDF文件第6页浏览型号AD8013AN的Datasheet PDF文件第7页浏览型号AD8013AN的Datasheet PDF文件第8页浏览型号AD8013AN的Datasheet PDF文件第9页浏览型号AD8013AN的Datasheet PDF文件第10页浏览型号AD8013AN的Datasheet PDF文件第12页 
AD8013  
1.5  
1.0  
+5V  
V
I
8k  
4k  
G = +2  
= 150Ω  
R
L
TO DISABLE PIN  
0.5  
10k  
–5V  
0
V
= +5V  
S
V
V
HIGH => AMPLIFIER ENABLED  
LOW => AMPLIFIER DISABLED  
I
I
–0.5  
–1.0  
–1.5  
–2.0  
V
= ±5V  
S
Figure 36. Level Shifting to Drive Disable Pins on Dual  
Supplies  
T he AD8013’s input stages include protection from the large  
differential input voltages that may be applied when disabled.  
Internal clamps limit this voltage to about ±3 V. The high input to  
output isolation will be maintained for voltages below this limit.  
1M  
10M  
100M  
1G  
FREQUENCY – Hz  
Figure 34. Closed-Loop Gain Matching vs. Frequency  
3:1 Video Multiplexer  
Wiring the amplifier outputs together will form a 3:1 mux with  
excellent switching behavior. Figure 37 shows a recommended  
configuration which results in –0.1 dB bandwidth of 35 MHz  
and OFF channel isolation of 60 dB at 10 MHz on ±5 V  
supplies. T he time to switch between channels is about 50 ns.  
Switching time is virtually unaffected by signal level.  
10  
G = +2  
8
R
= 150Ω  
L
6
4
2
V
= +5V  
S
V
= ±5V  
S
DELAY  
665Ω  
845Ω  
1.0  
G = +2  
= 150Ω  
+V  
4
S
0.5  
0
R
L
V
V
= ±5V  
S
6
5
84Ω  
= +5V  
S
7
–0.5  
–1.0  
DELAY  
MATCHING  
1
V
1
IN  
75Ω  
100k  
1M  
10M  
100M  
FREQUENCY – Hz  
DISABLE 1  
665Ω  
845Ω  
Figure 35. Group Delay and Group Delay Matching  
vs. Frequency, G = +2, RL = 150 Ω  
75Ω  
CABLE  
13  
12  
84Ω  
14  
V
OUT  
2
D isable Mode O per ation  
V
2
75Ω  
IN  
75Ω  
Pulling the voltage on any one of the Disable pins about 1.6 V  
up from the negative supply will put the corresponding  
amplifier into a disabled, powered down, state. In this  
condition, the amplifier’s quiescent current drops to about  
0.3 mA, its output becomes a high impedance, and there is  
a high level of isolation from input to output. In the case of  
the gain of two line driver for example, the impedance at the  
output node will be about the same as for a 1.6 kΩ resistor  
(the feedback plus gain resistors) in parallel with a 12 pF  
capacitor and the input to output isolation will be about  
66 dB at 5 MHz.  
DISABLE 2  
665Ω  
845Ω  
9
84Ω  
8
11  
10  
V
3
3
IN  
75Ω  
–V  
S
DISABLE 3  
Figure 37. A Fast Switching 3:1 Video Mux (Supply  
Bypassing Not Shown)  
Leaving the Disable pin disconnected (floating) will leave  
the corresponding amplifier operational, in the enabled  
state. The input impedance of the disable pin is about 40 kΩ  
in parallel with a few picofarads. When driven to 0 V, with  
the negative supply at –5 V, about 100 µA flows into the  
disable pin.  
200ns  
500mV  
100  
90  
When the disable pins are driven by complementary output  
CMOS logic, on a single 5 V supply, the disable and enable  
times are about 50 ns. When operated on dual supplies,  
level shifting will be required from standard logic outputs to  
the Disable pins. Figure 36 shows one possible method  
which results in a negligible increase in switching time.  
10  
0%  
5V  
Figure 38. Channel Switching Characteristic for the  
3:1 Mux  
REV. A  
–11–  
1...89101112

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AD8013AN 替代型号

型号 品牌 替代类型 描述 数据表
AD8013AN ADI

当前型号

 Single Supply, Low Power, Triple Video Amplifier
AD8056ARZ ADI

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