AD800/AD802
5.0V
C5
0.1
5.0V
C13 0.1
R13
154
R14
154
5.0V
R1
100
R2
100
R10
154
R9
154
R18
100
R17
100
C17 0.1
C14 0.1
C3 0.1
R15 100
R16 100
J1
J2
R5 100
R6 100
1
2
3
4
FRAC
FRAC
20
19
18
17
DATAOUT
DATAOUT
DATAOUT
FRAC
FRAC
DATAOUT
VCC2
5.0V
C15 0.1
C4 0.1
1
16
15
14
13
12
11
10
9
C9
0.1
SUBST
R12
154
2
3
C6 0.1
R19
130
R20
130
J3
R11
154
CLKOUT
CLKOUT
DATAIN
CLKOUT
CLKOUT
R7 100
5
6
16
15
14
13
12
DATAIN
VEE
J4
4
5
6
7
8
Z2
10H116
R23
VEE
R8 100
C7 0.1
R21
80.6
R22
80.6
130
R24
VCC1
R4
100
R3
7
8
VEE
130
C19
100
C12
0.1
5.0V
AVCC
VCC1
AVEE
C8
0.1
5.0V
0.1
C10
0.1
J5
5.0V
C11
9
DATAIN
DATAIN
CF1
CF2
C16
0.1
J6
CD
10
11
ASUBST
Z1
C20
0.1
AD800/802
IN
OUT
R26
80.6
R25
80.6
BYPASS
NETWORK
5.0V
C2
10µF
C21 0.1
5.0V
Figure 22. Evaluation Board Schem atic, Positive Supply
Table I. Evaluation Board, P ositive Supply: Com ponents List
D escription
Reference
D esignator
Quantity
R1–8, R15–18
R9–14
Resistor, 100 Ω, 1%
Resistor, 154 Ω, 1%
12
6
R19, 20, 23, 24
Resistor, 130 Ω, 1%
4
R21, 22, 25, 26
Resistor, 80.6 Ω, 1%
4
CD
C2
C3–C21
Z1
Capacitor, Loop Damping (See Specifications Page)
Capacitor, 10 µF, T antalum
Capacitor, 0.1 µF, Ceramic Chip
AD800/AD802
1
1
17
1
Z2
10H116, ECL Line Receiver
1
3.0
(A)
IN
TO
DEVICE
0.1µF
(A)
TO DEVICE
2.5
2.0
1.5
BEADS WITH ONE LOOP
(B)
IN
(B)
BYPASS
NETWORK
(A, B, C,
OR D)
TO
DEVICE
0.1µF
(C)
BEAD WITH
BEAD WITH
IN
ONE LOOP TWO LOOPS
(C)
IN
TO
DEVICE
C2
10µF
0.1µF
1.0
0.5
(D)
5.0V
BEAD WITH
TWO LOOPS TWO LOOPS
BEAD WITH
(D)
IN
TO
DEVICE
0.1µF
BYPASS NETWORK
COMPONENTS:
CAPACITOR ..........CERAMIC CHIP
FERRITE BEAD......1/4 IN. STACKPOLE CARBO 57-1392
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
NOISE – V p-p @ 311MHz
Figure 23. Bypass Network Schem es
Figure 24. AD802-155 Output J itter vs. Supply Noise
(PECL Configuration)
REV. B
–9–