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AD7912ARM PDF预览

AD7912ARM

更新时间: 2024-02-17 12:09:35
品牌 Logo 应用领域
亚德诺 - ADI 转换器模数转换器光电二极管
页数 文件大小 规格书
32页 386K
描述
2-Channel, 2.35 V to 5.25 V, 1 MSPS, 10-/12-Bit ADCs

AD7912ARM 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP,针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.52
最大模拟输入电压:5.25 V最小模拟输入电压:
最长转换时间:0.777 µs转换器类型:ADC, SUCCESSIVE APPROXIMATION
JESD-30 代码:R-PDSO-G8JESD-609代码:e4
长度:2.9 mm最大线性误差 (EL):0.0488%
湿度敏感等级:1模拟输入通道数量:2
位数:10功能数量:1
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C输出位码:BINARY
输出格式:SERIAL封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
认证状态:Not Qualified采样速率:1 MHz
采样并保持/跟踪并保持:TRACK座面最大高度:1.1 mm
标称供电电压:3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:1.6 mmBase Number Matches:1

AD7912ARM 数据手册

 浏览型号AD7912ARM的Datasheet PDF文件第4页浏览型号AD7912ARM的Datasheet PDF文件第5页浏览型号AD7912ARM的Datasheet PDF文件第6页浏览型号AD7912ARM的Datasheet PDF文件第8页浏览型号AD7912ARM的Datasheet PDF文件第9页浏览型号AD7912ARM的Datasheet PDF文件第10页 
AD7912/AD7922  
TIMING SPECIFICATIONS  
Guaranteed by characterization.  
All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.  
VDD = 2.35 V to 5.25 V; TA = TMIN to TMAX, unless otherwise noted.  
Table 3.  
Parameter  
Limit at TMIN  
TMAX  
,
Unit  
Description  
fSCLK  
10  
18  
kHz min2  
MHz max  
1
tCONVERT  
16 × tSCLK  
14 × tSCLK  
AD7922  
AD7912  
tQUIET  
t1  
30  
15  
ns min  
ns min  
ns min  
ns max  
ns max  
ns min  
ns min  
ns min  
ns min  
ns min  
ns max  
ns min  
µs max  
Minimum quiet time required between bus relinquish and start of next conversion  
Minimum CS pulse width  
t2  
10  
CS to SCLK setup time  
3
t3  
30  
Delay from CS until DOUT three-state is disabled  
DOUT access time after SCLK falling edge  
SCLK low pulse width  
SCLK high pulse width  
SCLK to DOUT valid hold time  
DIN setup time prior to SCLK falling edge  
DIN hold time after SCLK falling edge  
SCLK falling edge to DOUT three-state  
SCLK falling edge to DOUT three-state  
Power-up time from full power-down  
3
t4  
45  
0.4 tSCLK  
0.4 tSCLK  
10  
5
t5  
t6  
t7  
4
t8  
t9  
t10  
6
5
30  
10  
1
6
tPOWER-UP  
1 Mark/space ratio for SCLK input is 40/60 to 60/40.  
2 Minimum fSCLK at which specifications are guaranteed.  
3 Measured with the load circuit in Figure 2 and defined as the time required for the output to cross VIH or VIL voltage.  
4 Measured with a 50 pF load capacitor.  
5 T10 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated  
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t10, quoted in the timing characteristics is the true bus relinquish  
time of the part and is independent of the bus loading.  
6 See the Power-Up Time section.  
TIMING DIAGRAMS  
t7  
200µA  
I
OL  
SCLK  
DOUT  
TO OUTPUT  
PIN  
1.6V  
C
50pF  
L
V
IH  
V
IL  
200µA  
I
OH  
Figure 2. Load Circuit for Digital Output Timing Specifications  
Figure 4. Hold Time after SCLK Falling Edge  
t10  
t4  
SCLK  
SCLK  
DOUT  
V
V
IH  
1.6V  
DOUT  
IL  
Figure 3. Access Time after SCLK Falling Edge  
Figure 5. SCLK Falling Edge to DOUT Three-State  
Rev. 0 | Page 7 of 32  
 
 
 
 
 
 
 

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