AD7875KP-REEL

更新时间： 2024-02-12 00:14:08

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
20页	332K
描述
IC 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQCC28, PLASTIC, MO-047AB, LCC-28, Analog to Digital Converter

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AD7875KP-REEL 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	DIP
包装说明：	DIP,	针数：	24
Reach Compliance Code：	unknown	风险等级：	5.67
最大模拟输入电压：	5 V	最小模拟输入电压：
最长转换时间：	9 µs	转换器类型：	ADC, SUCCESSIVE APPROXIMATION
JESD-30 代码：	R-GDIP-T24	JESD-609代码：	e0
最大线性误差 (EL)：	0.0244%	湿度敏感等级：	NOT APPLICABLE
标称负供电电压：	-5 V	模拟输入通道数量：	1
位数：	12	功能数量：	1
端子数量：	24	最高工作温度：	125 °C
最低工作温度：	-55 °C	输出位码：	BINARY, 2'S COMPLEMENT BINARY
输出格式：	SERIAL, PARALLEL, 8 BITS, PARALLEL, WORD	封装主体材料：	CERAMIC, GLASS-SEALED
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	NOT APPLICABLE
采样速率：	0.1 MHz	采样并保持/跟踪并保持：	TRACK
座面最大高度：	5.08 mm	标称供电电压：	5 V
表面贴装：	NO	技术：	CMOS
温度等级：	MILITARY	端子面层：	TIN LEAD
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT APPLICABLE
宽度：	7.62 mm	Base Number Matches：	1

AD7875KP-REEL 数据手册

AD7870/AD7875/AD7876

P IN FUNCTIO N D ESCRIP TIO N

D IP

P in

P in No. Mnem onic

Function

BUSY/INT

CLK

Read. Active low logic input. T his input is used in conjunction with CS low to enable the data outputs.

Busy/Interrupt, Active low logic output indicating converter status. See timing diagrams.

Clock input. An external T T L-compatible clock may be applied to this input pin. Alternatively, tying this pin to

V_SSenables the internal laser-trimmed clock oscillator.

DB11/HBEN Data Bit 11 (MSB)/High Byte Enable. T he function of this pin is dependent on the state of the 12/8/CLK input (see

below). When 12-bit parallel data is selected, this pin provides the DB11 output. When byte data is selected, this pin

becomes the HBEN logic input HBEN is used for 8-bit bus interfacing. When HBEN is low, DB7/LOW to DB0/DB8

become DB7 to DB0. With HBEN high, DB7/LOW to DB0/DB8 are used for the upper byte of data (see T able I).

DB10/SSTRB Data Bit 10/Serial Strobe. When 12-bit parallel data is selected, this pin provides the DB10 output. SSTRB is an

active low open-drain output that provides a strobe or framing pulse for serial data. An external 4.7 kΩ pull-up

resistor is required on SSTRB.

DB9/SCLK

Data Bit 9/Serial Clock. When 12-bit parallel data is selected, this pin provides the DB9 output. SCLK is the gated

serial clock output derived from the internal or external ADC clock. If the 12/8/CLK input is at –5 V, then SCLK

runs continuously. If 12/8/CLK is at 0 V, then SCLK is gated off after serial transmission is complete. SCLK is an

open-drain output and requires an external 2 kΩ pull-up resistor.

DB8/SDAT A Data Bit 8/Serial Data. When 12-bit parallel data is selected, this pin provides the DB8 output. SDAT A is an open-

drain serial data output which is used with SCLK and SSTRB for serial data transfer. Serial data is valid on the fall-

ing edge of SCLK while SSTRB is low. An external 4.7 kΩ pull-up resistor is required on SDAT A.

8–11

DB7/LOW–

DB4/LOW

T hree-state data outputs controlled by CS and RD. T heir function depends on the 12/8/CLK and HBEN inputs.

With 12/8/CLK high, they are always DB7–DB4. With 12/8/CLK low or –5 V, their function is controlled by HBEN

(see T able I).

DGND

Digital Ground. Ground reference for digital circuitry.

13–16

DB3/DB11–

DB0/DB8

T hree-state data outputs which are controlled by CS and RD. T heir function depends on the 12/8/CLK and HBEN

inputs. With 12/8/CLK high, they are always DB3–DB0. With 12/8/CLK low or –5 V, their function is controlled by

HBEN (see T able I).

Table I. O utput D ata for Byte Inter facing

HBEN

HIGH

LOW

DB7/LOW DB6/LOW DB5/LOW DB4/LOW DB3/DB11

DB2/DB10 DB1/DB9 DB0/DB8

LOW

DB7

LOW

DB6

LOW

DB5

LOW

DB4

DB11(MSB)

DB3

DB10

DB2

DB9

DB1

DB8

DB0 (LSB)

V_DD

Positive Supply, +5 V ± 5%.

Analog Ground. Ground reference for track/hold, reference and DAC.

AGND

REF OUT

V_IN

Voltage Reference Output. T he internal 3 V reference is provided at this pin. T he external load capability is 500 µA.

Analog Input. T he analog input range is ±3 V for the AD7870, ±10 V for the AD7876 and 0 V to +5 V for the AD7875.

Negative Supply, –5 V ± 5%.

V_SS

12/8/CLK

T hree Function Input. Defines the data format and serial clock format. With this pin at +5 V, the output data for-

mat is 12-bit parallel only. With this pin at 0 V, either byte or serial data is available and SCLK is not continuous.

With this pin at –5 V, either byte or serial data is again available but SCLK is now continuous.

CONVST

Convert Start. A low to high transition on this input puts the track/hold into its hold mode and starts conversion.

T his input is asynchronous to the CLK input.

Chip Select. Active low logic input. T he device is selected when this input is active. With CONVST tied low, a new

conversion is initiated when CS goes low.

P IN CO NFIGURATIO NS¹

D IP and SO IC ²

P LCC ²

¹PIN CONFIGURATIONS ARE THE SAME FOR

THE AD7875 AND AD7876.

²THE AD7870 AND AD7875 ARE AVAILABLE IN

DIP AND PLCC; THE AD7870A IS AVAILABLE IN

PLASTIC DIP; THE AD7875 AND AD7876 ARE

AVAILABLE IN SOIC AND DIP.

REV. B

–6–

1...3 4 567 8 9...20

中文翻译

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