AD783AQ

更新时间： 2024-01-26 17:41:16

品牌	Logo	应用领域
亚德诺 - ADI		放大器
页数	文件大小	规格书
8页	134K
描述
Complete Very High Speed Sample-and-Hold Amplifier

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技术参数
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AD783AQ 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	DIP	包装说明：	MINI, CERDIP-8
针数：	8	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.33.00.01
风险等级：	5.73	Is Samacsys：	N
最长采集时间：	0.25 µs	标称采集时间：	0.15 µs
放大器类型：	SAMPLE AND HOLD CIRCUIT	最大模拟输入电压：	2.5 V
最小模拟输入电压：	-2.5 V	最大下降率：	1 V/s
JESD-30 代码：	R-GDIP-T8	JESD-609代码：	e0
负供电电压上限：	-6.5 V	标称负供电电压 (Vsup)：	-5 V
功能数量：	1	端子数量：	8
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	CERAMIC, GLASS-SEALED	封装代码：	DIP
封装等效代码：	DIP8,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	+-5 V	认证状态：	Not Qualified
采样并保持/跟踪并保持：	SAMPLE	座面最大高度：	5.08 mm
子类别：	Sample and Hold Circuits	最大压摆率：	14 mA
供电电压上限：	6.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	NO	技术：	BIMOS
温度等级：	MILITARY	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.62 mm	Base Number Matches：	1

AD783AQ 数据手册

AD783

T he AD783 does not provide separate analog and digital ground

leads as is the case with most A-to-D converters. T he common

pin is the single ground terminal for the device. It is the refer-

ence point for the sampled input voltage and the held output

voltage and also the digital ground return path. T he common

pin should be connected to the reference (analog) ground of the

A-to-D converter with a separate ground lead. Since the analog

and digital grounds in the AD783 are connected internally, the

common pin should also be connected to the digital ground,

which is usually tied to analog common at the A-to-D converter.

Figure 3 illustrates the recommended decoupling and grounding

practice.

T he accuracy in sampling high frequency signals is also

constrained by the distortion and noise created by the

sample-and-hold. T he level of distortion increases with

frequency and reduces the “effective number of bits” of the

conversion.

Measurements of Figures 6 and 7 were made using a 14-bit

A/D converter with V_IN= 5 V p-p and a sample frequency of

100 kSPS.

1/2 BIT @

8 BITS

NO ISE CH ARACTERISTICS

Designers of data conversion circuits must also consider the

effect of noise sources on the accuracy of the data acquisition

system. A sample-and-hold amplifier that precedes the A-to-D

converter introduces some noise and represents another source

of uncertainty in the conversion process. T he noise from the

AD783 is specified as the total output noise, which includes

both the sampled wideband noise of the SHA in addition to the

band limited output noise. T he total output noise is the rms

sum of the sampled dc uncertainty and the hold mode noise. A

plot of the total output noise vs. the equivalent input bandwidth

of the converter being used is given in Figure 4.

0.1%

1/2 BIT @

10 BITS

1/2 BIT @

12 BITS

APERTURE JITTER TYPICAL AT 20ps

0.01%

1/2 BIT @

14 BITS

10k

100k

FREQUENCY – Hz

300

200

100

Figure 5. Error Magnitude vs. Frequency

–65

–70

–75

–80

–85

–90

10k

100k

10M

FREQUENCY – Hz

–95

100

10k

100k

Figure 4. RMS Noise vs. Input Bandwidth of ADC

FREQUENCY – Hz

D RIVING TH E ANALO G INP UTS

Figure 6. Total Harm onic Distortion vs. Frequency

For best performance, it is important to drive the AD783 analog

input from a low impedance signal source. T his enhances the

sampling accuracy by minimizing the analog and digital cross-

talk. Signals which come from higher impedance sources (e.g.,

over 5 kΩ) will have a relatively higher level of crosstalk. For

applications where signals have high source impedance, an

operational amplifier buffer in front of the AD783 is required.

T he AD711 (precision BiFET op amp) is recommended for

these applications.

H IGH FREQ UENCY SAMP LING

Aperture jitter and distortion are the primary factors which limit

frequency domain performance of a sample-and-hold amplifier.

Aperture jitter modulates the phase of the hold command and

produces an effective noise on the sampled analog input. T he

magnitude of the jitter induced noise is directly related to the

frequency of the input signal.

10k

100k

FREQUENCY – Hz

A graph showing the magnitude of the jitter induced error vs.

frequency of the input signal is given in Figure 5.

Figure 7. Signal/(Noise and Distortion) vs. Frequency

REV. A

–7–

1...4 5 678

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