AD783AQ

更新时间： 2024-01-22 08:53:46

品牌	Logo	应用领域
亚德诺 - ADI		放大器
页数	文件大小	规格书
8页	134K
描述
Complete Very High Speed Sample-and-Hold Amplifier

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AD783AQ 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	DIP	包装说明：	MINI, CERDIP-8
针数：	8	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.33.00.01
风险等级：	5.73	Is Samacsys：	N
最长采集时间：	0.25 µs	标称采集时间：	0.15 µs
放大器类型：	SAMPLE AND HOLD CIRCUIT	最大模拟输入电压：	2.5 V
最小模拟输入电压：	-2.5 V	最大下降率：	1 V/s
JESD-30 代码：	R-GDIP-T8	JESD-609代码：	e0
负供电电压上限：	-6.5 V	标称负供电电压 (Vsup)：	-5 V
功能数量：	1	端子数量：	8
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	CERAMIC, GLASS-SEALED	封装代码：	DIP
封装等效代码：	DIP8,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	+-5 V	认证状态：	Not Qualified
采样并保持/跟踪并保持：	SAMPLE	座面最大高度：	5.08 mm
子类别：	Sample and Hold Circuits	最大压摆率：	14 mA
供电电压上限：	6.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	NO	技术：	BIMOS
温度等级：	MILITARY	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.62 mm	Base Number Matches：	1

AD783AQ 数据手册

AD783

D YNAMIC P ERFO RMANCE

HOLD – V ), mV

OUT

T he AD783 is compatible with 12-bit A-to-D converters in

terms of both accuracy and speed. T he fast acquisition time, fast

hold settling time and good output drive capability allow the

AD783 to be used with high speed, high resolution A-to-D

converters like the AD671 and AD7586. T he AD783’s fast

acquisition time provides high throughput rates for multichannel

data acquisition systems. T ypically, the AD783 can acquire a

5 V step in less than 250 ns. Figure 1 shows the settling

accuracy as a function of acquisition time.

, VOLTS

+2.5

–2.5

NONLINEARITY

0.08

HOLD MODE OFFSET

–1

GAIN ERROR

0.06

0.04

Figure 2. Hold Mode Offset, Gain Error and Nonlinearity

0.02

For applications where it is important to obtain zero offset, the

hold mode offset may be nulled externally at the input to the

A-to-D converter. Adjustment of the offset may be accom-

plished through the A-to-D itself or by an external amplifier

with offset nulling capability (e.g., AD711). T he offset will

change less than 0.5 mV over the specified temperature range.

250

500

ACQUISITION TIME – ns

Figure 1. V_OUTSettling vs. Acquisition Tim e

T he hold settling determines the required time, after the hold

command is given, for the output to settle to its final specified

accuracy. T he typical settling behavior of the AD783 is 150 ns.

T he settling time of the AD783 is sufficiently fast to allow the

SHA, in most cases, to directly drive an A-to-D converter

without the need for an added “start convert” delay.

SUP P LY D ECO UP LING AND GRO UND ING

CO NSID ERATIO NS

As with any high speed, high resolution data acquisition system,

the power supplies should be well regulated and free from

excessive high frequency noise (ripple). T he supply connection

to the AD783 should also be capable of delivering transient

currents to the device. T o achieve the specified accuracy and

dynamic performance, decoupling capacitors must be placed

directly at both the positive and negative supply pins to com-

mon. Ceramic type 0.1 µF capacitors should be connected from

V_CCand V_EEto common.

H O LD MO D E O FFSET

T he dc accuracy of the AD783 is determined primarily by the

hold mode offset. T he hold mode offset refers to the difference

between the final held output voltage and the input signal at the

time the hold command is given. T he hold mode offset arises

from a voltage error introduced onto the hold capacitor by

charge injection of the internal switches. T he nominal hold

mode offset is specified for a 0 V input condition. Over the in-

put range of –2.5 V to +2.5 V, the AD783 is also characterized

for an effective gain error and nonlinearity of the held value, as

shown in Figure 2. As indicated by the AD783 specifications,

the hold mode offset is very stable over temperature.

ANALOG

P.S.

DIGITAL

P.S.

+5V

–5V

+5V

0.1µF 0.1µF

1µF

INPUT

DIGITAL

DATA

OUTPUT

ANALOG-TO-DIGITAL

CONVERTER

AD783

SIGNAL GROUND

Figure 3. Basic Grounding and Decoupling Diagram

–6–

REV. A

1...3 4 567 8

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