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AD783AQ PDF预览

AD783AQ

更新时间: 2024-01-08 08:09:26
品牌 Logo 应用领域
亚德诺 - ADI 放大器
页数 文件大小 规格书
8页 134K
描述
Complete Very High Speed Sample-and-Hold Amplifier

AD783AQ 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:MINI, CERDIP-8
针数:8Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.33.00.01
风险等级:5.73Is Samacsys:N
最长采集时间:0.25 µs标称采集时间:0.15 µs
放大器类型:SAMPLE AND HOLD CIRCUIT最大模拟输入电压:2.5 V
最小模拟输入电压:-2.5 V最大下降率:1 V/s
JESD-30 代码:R-GDIP-T8JESD-609代码:e0
负供电电压上限:-6.5 V标称负供电电压 (Vsup):-5 V
功能数量:1端子数量:8
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP8,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:+-5 V认证状态:Not Qualified
采样并保持/跟踪并保持:SAMPLE座面最大高度:5.08 mm
子类别:Sample and Hold Circuits最大压摆率:14 mA
供电电压上限:6.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:BIMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

AD783AQ 数据手册

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AD783  
O utput D r ive Cur r ent—T he maximum current the SHA can  
source (or sink) while maintaining a change in hold mode offset  
of less than 2.5 mV.  
D EFINITIO NS O F SP ECIFICATIO NS  
Acquisition Tim e—T he length of time that the SHA must  
remain in the sample mode in order to acquire a full-scale input  
step to a given level of accuracy.  
Signal-To-Noise and D istor tion (S/N+D ) Ratio—S/N+D is  
the ratio of the rms value of the measured input signal to the  
rms sum of all other spectral components below the Nyquist  
frequency, including harmonics but excluding dc. T he value for  
S/N+D is expressed in decibels.  
Sm all Signal Bandwidth—T he frequency at which the held  
output amplitude is 3 dB below the input amplitude, under an  
input condition of a 100 mV p-p sine wave.  
Full P ower Bandwidth—T he frequency at which the held  
output amplitude is 3 dB below the input amplitude, under an  
input condition of a 5 V p-p sine wave.  
Total H ar m onic D istor tion (TH D )—T HD is the ratio of the  
rms sum of the first six harmonic components to the rms value  
of the measured input signal and is expressed in decibels.  
Effective Aper tur e D elay—T he difference between the switch  
delay and the analog delay of the SHA channel. A negative  
number indicates that the analog portion of the overall delay is  
greater than the switch portion. T his effective delay represents  
the point in time, relative to the hold command, that the input  
signal will be sampled.  
Inter m odulation D istor tion (IMD )—With inputs consisting  
of sine waves at two frequencies, fa and fb, any device with  
nonlinearities will create distortion products, of order (m+n), at  
sum and difference frequency of mfa±nfb, where m, n = 0, 1, 2,  
3. . . . Intermodulation terms are those for which m or n is not  
equal to zero. For example, the second order terms are (fa+fb)  
and (fa–fb), and the third order terms are (2fa+fb), (2fa–fb),  
(fa+2fb) and (fa–2fb). T he IMD products are expressed as the  
decibel ratio of the rms sum of the measured input signals to the  
rms sum of the distortion terms. T he two signals are of equal  
amplitude, and peak value of their sums is –0.5 dB from full  
scale. T he IMD products are normalized to a 0 dB input signal.  
Aper tur e Jitter—T he variations in aperture delay for  
successive samples. Aperture jitter puts an upper limit on the  
maximum frequency that can be accurately sampled.  
H old Settling Tim e—T he time required for the output to  
settle to within a specified level of accuracy of its final held value  
after the hold command has been given.  
D r oop Rate—T he drift in output voltage while in the hold  
mode.  
FUNCTIO NAL D ESCRIP TIO N  
T he AD783 is a complete, high speed sample-and-hold  
amplifier that provides high speed sampling to 12-bit accuracy  
in 250 ns.  
Feedthr ough—T he attenuated version of a changing input  
signal that appears at the output when the SHA is in the hold  
mode.  
T he AD783 is completely self-contained, including an on-chip  
hold capacitor, and requires no external components or adjust-  
ments to perform the sampling function. Both input and output  
are treated as a single-ended signal, referred to common.  
H old Mode O ffset—T he difference between the input signal  
and the held output. T his offset term applies only in the hold  
mode and includes the error caused by charge injection and all  
other internal offsets. It is specified for an input of 0 V.  
T he AD783 utilizes a proprietary circuit design which includes a  
self-correcting architecture. T his sample-and-hold circuit  
corrects for internal errors after the hold command has been  
given, by compensating for amplifier gain and offset errors, and  
charge injection errors. Due to the nature of the design, the  
SHA output in the sample mode is not intended to provide an  
accurate representation of the input. However, in hold mode,  
the internal circuitry is reconfigured to produce an accurately  
held version of the input signal. Below is a block diagram of the  
AD783.  
Sam ple Mode O ffset—T he difference between the input and  
output signals when the SHA is in the sample mode.  
Nonlinear ity—T he deviation from a straight line on a plot of  
input vs. (held) output as referenced to a straight line drawn  
between endpoints, over an input range of –2.5 V and +2.5 V.  
Gain Er r orDeviation from a gain of +1 on the transfer  
function of input vs. held output.  
P ower Supply Rejection Ratio—A measure of change in the  
held output voltage for a specified change in the positive or  
negative supply.  
1
2
3
4
8
OUT  
V
Sam pled D C Uncer tainty—T he internal rms SHA noise that  
is sampled onto the hold capacitor.  
CC  
7
6
5
IN  
COMMON  
NC  
S/H  
NC  
X1  
H old Mode Noise—T he rms noise at the output of the SHA  
while in the hold mode, specified over a given bandwidth.  
Total O utput Noise—T he total rms noise that is seen at the  
output of the SHA while in the hold mode. It is the rms  
summation of the sampled dc uncertainty and the hold mode  
noise.  
AD783  
V
EE  
NC = NO CONNECT  
Functional Block Diagram  
REV. A  
–5–  

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