AD7821
P IN FUNCTIO N D ESCRIP TIO N
O P ERATING SEQ UENCE
T he AD7821 has two operating modes. T he RD mode allows a
conversion to be started and data to be read with a single, ex-
tended, READ operation (i.e., CS and RD are taken low). T he
conversion process is timed out by internal one-shots. T he WR-
RD mode uses WR to start a conversion and RD to read the
data and allows the conversion timing to be externally con-
trolled. T he operating sequence for the WR-RD mode is shown
in Figure 3.
P in
Mnem onic D escription
1
VIN
Analog Input: Range VREF(–) ≤ VIN
REF(+)
T hree-State Data Output (LSB).
≤
V
2
DB0
3–5
6
DB1–DB3 T hree-State Data Outputs.
WR/RDY
WRIT E control input/READY status
output. See Digital Interface section.
7
MODE
Mode Selection Input. It determines
whether the device operates in the
WR-RD or RD mode. T his input is in-
ternally pulled low through a 50 µA
current source. See Digital Interface
section.
8
9
RD
READ Input. RD must be low to access
data from the part. See Digital Interface
section.
Figure 3. Operating Sequence (WR-RD Mode)
INT
INT ERRUPT Output. INT going low
indicates that the conversion is complete.
INT returns high on the rising edge of
CS or RD. See Digital Interface section.
A conversion is initiated and the analog input signal (VIN)
sampled on the falling edge of WR (falling edge of RD, RD
mode). A setup time (tP, delay time between conversions) of
350 ns is required prior to this falling edge. See Digital Interface
section for more details. When WR is low, the internal MS
(most significant) ADC compares the sampled analog input with
the reference ladder to provide the 4 MS data bits. A minimum
of 250 ns is required for this comparison. On the rising edge of
WR, the MS data result is latched internally and the LS (least
significant) conversion begins, to yield the 4 LS data bits. INT
goes low typically 380 ns after the rising edge of WR. T his indi-
cates the LS conversion is complete and that both the LS and
MS data results are latched into the output buffer. RD going
low then enables the output data. If a faster conversion time is
required, the RD line can be brought low 250 ns after WR goes
high. T his latches both the LS and MS data bits and outputs the
conversion result on DB0–DB7.
10
11
GND
Ground.
VREF(–)
Lower limit of reference span.
Range: VSS ≤ VREF(–) ≤ VREF(+).
12
13
VREF(+)
Upper limit of reference span.
Range: VREF(–) < VREF(+) ≤ VDD
.
CS
Chip Select Input. T he device is selected
when this input is low.
14–16 DB4–DB6 T hree-State Data Outputs.
17
18
DB7
T hree-State Data Output (MSB).
OFL
Overflow Output. If the analog input is
higher than (VREF(+) – 1/2 LSB), OFL
will be low at the end of conversion. It is
a non-three-state output which can be
used to cascade 2 or more devices to
increase resolution.
REFERENCE AND INP UT
T he VREF(–) and VREF(+) reference inputs on the AD7821 are
fully differential and define the zero and full-scale input range of
the ADC. T he transfer characteristic of the part is defined by
the integer value of the following expression:
19
20
VSS
Negative supply voltage.
VSS = 0 V; Unipolar Operation.
VSS = –5 V; Bipolar Operation.
VDD
Positive supply voltage, +5 V.
VIN −VREF (−)
VREF (+) −VREF (−)
Data (LSBs) = 256
+ 0.5
CIRCUIT INFO RMATIO N
BASIC D ESCRIP TIO N
As a result, the analog input (VIN) Of the device can easily be set
up to provide both unipolar and bipolar operation. T he data
output code for unipolar and bipolar operation is Natural Binary
and Offset Binary, respectively.
T he AD7821 uses a half flash conversion technique (see Func-
tional Block Diagram), whereby two 4-bit flash ADCs are used
to achieve an 8-bit result. Each 4-bit flash ADC contains 15
comparators, which compare an unknown input voltage to the
reference ladder, to achieve a 4-bit result. T he MS (most signifi-
cant) flash ADC converts an unknown analog input voltage
(VIN) to provide the 4 MS data bits. An internal DAC, driven by
the 4 MS data bits, then recreates an analog approximation of
the input voltage. T he DAC output voltage is subtracted from
the analog input, and the difference is converted by the LS
(least significant) ADC to provide the 4 LS data bits. T he MS
flash ADC also has one additional comparator to detect over-
range on the analog input.
T he span of the analog input voltage can easily be varied.
By reducing the reference span, VREF(+) – VREF(–), to less than
5 V the sensitivity of the converter can be increased (i.e., if
VREF = 2 V then 1 LSB = 7.8 mV). T he reference flexibility also
allows the input span for unipolar operation to be offset from
zero (VREF(–) > GND). Additionally, the input/reference ar-
rangement facilitates ratiometric operation.
Figures 4 and 5 show some configurations which are possible.
For minimum noise a 47 µF capacitor in parallel with a 0.1 µF
capacitor should be connected between the reference inputs and
GND.
–6–
REV. A
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