AD674B/AD774B
(For all grades TMIN to TMAX with VCC = +15 V ꢂ 10% or +12 V ꢂ 5%, VLOGIC = +5 V ꢂ 10%,
VEE = –15 V ꢂ 10% or –12 V ꢂ 5%, unless otherwise noted.)
DIGITAL SPECIFICATIONS
Parameter
Test Conditions
Min
Max
Unit
LOGIC INPUTS
VIH
VIL
IIH
IIL
CIN
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
2.0
VLOGIC + 0.5
V
V
µA
µA
pF
–0.5
–10
–10
+0.8
+10
+10
10
VIN = VLOGIC
VIN = 0 V
LOGIC OUTPUTS
VOH
VOL
IOZ
High Level Output Voltage
IOH = 0.5 mA
IOL = 1.6 mA
VIN = 0 to VLOGIC
2.4
V
V
µA
pF
Low Level Output Voltage
High-Z Leakage Current
High-Z Output Capacitance
0.4
+10
10
–10
COZ
(For all grades TMIN to TMAX with VCC = +15 V ꢂ 10% or +12 V ꢂ 5%,
VLOGIC = +5 V ꢂ 10%, VEE = –15 V ꢂ 10% or –12 V ꢂ 5%, unless otherwise noted.)
SWITCHING SPECIFICATIONS
CONVERTER START TIMING (Figure 1)
CE
tHEC
tHSC
J, K, A, B Grades
Symbol Min Typ Max Min Typ Max Unit
T Grade
tSSC
tSRC tHRC
CS
Parameter
Conversion Time
R/C
8-Bit Cycle (AD674B) tC
12-Bit Cycle (AD674B) tC
8-Bit Cycle (AD774B) tC
12-Bit Cycle (AD774B) tC
6
9
4
6
8
10
6
9
4
6
8
10
µs
µs
µs
µs
12 15
5
7.3
12 15
5
7.3
A
0
tHAC
6
8
200
6
8
tSAC
STS Delay from CE
CE Pulsewidth
CS to CE Setup
tDSC
tHEC
tSSC
225 ns
STS
50
50
50
50
50
0
50
50
50
50
50
0
ns
ns
ns
ns
ns
ns
ns
tC
tDSC
HIGH
IMPEDANCE
DB11 – DB0
CS Low During CE High tHSC
R/C to CE Setup tSRC
R/C LOW During CE High tHRC
A0 to CE Setup tSAC
A0 Valid During CE High tHAC
Figure 1. Convert Start Timing
CE
50
50
tHSR
tSSR
CS
READ TIMING—FULL CONTROL MODE (Figure 2)
J, K, A, B Grades T Grade
R/C
tSRR
tHRR
Parameter
Symbol Min Typ Max Min Typ Max Unit
A
0
tHAR
tSAR
Access Time
1
CL = 100 pF
tDD
75 150
150
75 150 ns
STS
tHD
DATA
VALID
Data Valid After CE Low tHD
252
203
252
154
ns
ns
150 ns
HIGH
IMPEDANCE
HIGH
DB11 – DB0
IMPEDANCE
tDD
5
Output Float Delay
CS to CE Setup
R/C to CE Setup
tHL
tHL
tSSR
tSRR
tSAR
tHSR
tHRR
tHAR
50
0
50
0
0
50
50
0
50
0
0
50
ns
ns
ns
ns
ns
ns
Figure 2. Read Cycle Timing
5V
A0 to CE Setup
CS Valid After CE Low
R/C High After CE Low
A0 Valid After CE Low
3kꢀ
DB
DB
N
N
100pF
100pF
3kꢀ
NOTES
HIGH-Z TO LOGIC 1
HIGH-Z TO LOGIC 0
1tDD is measured with the load circuit of Figure 3a and is defined as the time required
for an output to cross 0.4 V or 2.4 V.
High-Z to Logic 1
High-Z to Logic 0
20°C to TMAX
3At –40°C.
4At –55°C.
.
Figure 3a. Load Circuit for Access Time Test
5V
5tHL is defined as the time required for the data lines to change 0.5 V when loaded with
the circuit of Figure 3b.
3kꢀ
DB
DB
N
N
Specifications shown in boldface are tested on all devices at final electrical test with
worst case supply voltages at TMIN, 25°C, and TMAX. Results from those tests are used
to calculate outgoing quality levels. All min and max specifications are guaranteed,
although only those shown in boldface are tested.
100pF
100pF
3kꢀ
LOGIC 1 TO HIGH-Z
LOGIC 0 TO HIGH-Z
Logic 1 to High-Z
Logic 0 to High-Z
Specifications subject to change without notice.
Figure 3b. Load Circuit for Output Float Delay Test
REV. C
–3–
5秒后页面跳转
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