AD7745/AD7746
The offset calibration register is reloaded by the default value at
power-on or after reset. Therefore, if the offset calibration is not
repeated after each system power-up, the calibration coefficient
value should be stored by the host controller and reloaded as
part of the AD7745/AD7746 setup.
PARASITIC SERIAL RESISTANCE
R
S1
DATA
CIN
CDC
On the AD7746, the register is shared by the two capacitive
channels. If the capacitive channels need to be offset calibrated
individually, the host controller software should read the
AD7746 capacitive offset calibration register values after
performing the offset calibration on individual channels and
then reload the values back to the AD7746 before executing a
conversion on a different channel.
C
X
R
S2
EXC
Figure 39. Parasitic Serial Resistance
The AD7745/AD7746 CDC result is affected by a resistance in
series with the measured capacitance. The total serial resistance,
which refers to RS1 + RS2 on ꢀigure 39, should be less than 1 kΩ
for the specified performance. See typical performance charac-
teristics shown in ꢀigure 15.
INTERNAL TEMPERATURE SENSOR
INTERNAL TEMPERATURE SENSOR
V
DD
I
N × I
CLOCK
GENERATOR
CAPACITIVE GAIN CALIBRATION
DATA
DIGITAL
FILTER
AND
The AD7745/AD7746 gain is factory calibrated for the full scale
of ±4.±96 pꢀ in the production for each part individually. The
factory gain coefficient is stored in a one-time programmable
(OTP) memory and is copied to the capacitive gain register at
power-up or after reset.
24-BIT Σ-∆
∆V
BE
MODULATOR
SCALING
VOLTAGE
REFERENCE
Figure 40. Internal Temperature Sensor
The gain can be changed by executing a capacitance gain
calibration mode, for which an external full-scale capacitance
needs to be connected to the capacitance input, or by writing a
user value to the capacitive gain register. This change would be
only temporary and the factory gain coefficient would be
reloaded back after power-up or reset. The part is tested and
specified only for use with the default factory calibration
coefficient.
The temperature sensing method used in the AD7745/AD7746
is to measure a difference in ∆VBE voltage of a transistor
operated at two different currents (see ꢀigure 4±). The ∆VBE
change with temperature is linear and can be expressed as
KT
q
∆VBE = (nf )
× ln(N)
where:
CAPACITIVE SYSTEM OFFSET CALIBRATION
K is Boltzmann’s constant (1.38 × 1±–23).
T is the absolute temperature in Kelvin.
q is the charge on the electron (1.6 × 1±–19 coulombs).
N is the ratio of the two currents.
The capacitive offset is dominated by the parasitic offset in the
application, such as the initial capacitance of the sensor, any
parasitic capacitance of tracks on the board, and the capacitance
of any other connections between the sensor and the CDC.
Therefore, the AD7745/AD7746 are not factory calibrated for
capacitive offset. It is the user’s responsibility to calibrate the
system capacitance offset in the application.
nf is the ideality factor of the thermal diode.
The AD7745/AD7746 uses an on-chip transistor to measure the
temperature of the silicon chip inside the package. The Σ-Δ
ADC converts the ∆VBE to digital, the data are scaled using
factory calibration coefficients, thus the output code is
proportional to temperature:
Any offset in the capacitance input larger than ±1 pꢀ should
first be removed using the on-chip CAPDACs. The small offset
within ±1 pꢀ can then be removed by using the capacitance
offset calibration register.
Code
2±48
One method of adjusting the offset is to connect a zero-scale
capacitance to the input and execute the capacitance offset
calibration mode. The calibration sets the midpoint of the
±4.±96 pꢀ range (that is, Output Code ±x8±±±±±) to that
zero-scale input.
Temperature
(
°C
)
=
− 4±96
The AD7745/AD7746 has a low power consumption resulting
in only a small effect due to the part self-heating (less than
±.5°C at VDD = 5 V).
Another method would be to calculate and write the offset cali-
bration register value, the LSB is value 31.25 aꢀ (4.±96 pꢀ/217).
Rev. 0| Page 23 of 28
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