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AD7705BR-REEL7

更新时间： 2024-01-02 23:42:14
品牌 Logo 应用领域
亚德诺 - ADI 转换器模数转换器光电二极管
页数 文件大小 规格书
44页 401K
描述
3 V/5 V, 1 mW, 2-/3-Channel, 16-Bit, Sigma-Delta ADCs

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AD7705BR-REEL7 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SOIC包装说明：0.300 INCH, MS-013AA, SOIC-16
针数：16Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.26Is Samacsys：N
最大模拟输入电压：2.5 V最小模拟输入电压：-2.5 V
转换器类型：ADC, DELTA-SIGMAJESD-30 代码：R-PDSO-G16
JESD-609代码：e0长度：10.3 mm
最大线性误差 (EL)：0.003%湿度敏感等级：1
模拟输入通道数量：2位数：16
功能数量：1端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
输出位码：BINARY, OFFSET BINARY输出格式：SERIAL
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：240
电源：3/5 V认证状态：Not Qualified
采样速率：0.0192 MHz座面最大高度：2.65 mm
子类别：Other Converters标称供电电压：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：7.5 mmBase Number Matches：1

AD7705BR-REEL7 数据手册

 浏览型号AD7705BR-REEL7的Datasheet PDF文件第7页浏览型号AD7705BR-REEL7的Datasheet PDF文件第8页浏览型号AD7705BR-REEL7的Datasheet PDF文件第9页浏览型号AD7705BR-REEL7的Datasheet PDF文件第11页浏览型号AD7705BR-REEL7的Datasheet PDF文件第12页浏览型号AD7705BR-REEL7的Datasheet PDF文件第13页 
AD7705/AD7706  
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
SCLK  
MCLK IN  
MCLK OUT  
CS  
GND  
SCLK  
MCLK IN  
MCLK OUT  
CS  
1
2
3
4
5
6
7
8
16 GND  
15  
V
DD  
V
DD  
DIN  
AD7706  
TOP VIEW  
(Not to Scale)  
14 DIN  
AD7705  
DOUT  
13 DOUT  
12 DRDY  
11 AIN2(–)  
10 REF IN(–)  
TOP VIEW  
RESET  
AIN1  
DRDY  
(Not to Scale)  
RESET  
AIN3  
AIN2(+)  
AIN1(+)  
AIN1(–)  
AIN2  
REF IN(–)  
REF IN(+)  
COMMON  
9
REF IN(+)  
Figure 3. AD7705 Pin Configuration  
Figure 4. AD7706 Pin Configuration  
Table 4. Pin Function Descriptions  
Mnemonic  
AD7705 AD7706  
Pin No.  
Description  
1
SCLK  
SCLK  
Serial Clock. An external serial clock is applied to the Schmitt-triggered logic input to access serial  
data from the AD7705/AD7706. This serial clock can be a continuous clock with all data transmitted in  
a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information  
transmitted to the AD7705/AD7706 in smaller batches of data.  
2
3
MCLK IN  
MCLK IN  
Master Clock Signal. This can be provided in the form of a crystal/resonator or external clock. A  
crystal/resonator can be tied across the Pin MCLK IN and Pin MCLK OUT. Alternatively, the MCLK IN  
pin can be driven with a CMOS-compatible clock with the MCLK OUT pin left unconnected. The parts  
can be operated with clock frequencies in the range of 500 kHz to 5 MHz.  
MCLK OUT MCLK OUT When the master clock for these devices is a crystal/resonator, the crystal/resonator is connected  
between Pin MCLK IN and Pin MCLK OUT. If an external clock is applied to Pin MCLK IN, Pin MCLK OUT  
provides an inverted clock signal. This clock can be used to provide a clock source for external  
circuitry and is capable of driving 1 CMOS load. If the user does not require this clock externally, Pin  
MCLK OUT can be turned off via the CLKDIS bit of the clock register. This ensures that the part does  
not unnecessarily burn power driving capacitive loads on Pin MCLK OUT.  
4
5
CS  
CS  
Chip Select. Active low logic input used to select the AD7705/AD7706. With this input hardwired low,  
the AD7705/AD7706 can operate in its 3-wire interface mode with Pin SCLK, Pin DIN, and Pin DOUT  
used to interface to the device. The CS pin can be used to select the device communicating with the  
AD7705/AD7706.  
Logic Input. Active low input that resets the control logic, interface logic, calibration coefficients,  
digital filter, and analog modulator of the parts to power-on status.  
RESET  
RESET  
6
7
8
AIN2(+)  
AIN1(+)  
AIN1(−)  
AIN1  
AIN2  
COMMON  
Positive Input of the Differential Analog Input Pair AIN2(+)/AIN2(−) for AD7705. Channel 1 for AD7706.  
Positive Input of the Differential Analog Input Pair AIN1(+)/AIN1(−) for AD7705. Channel 2 for AD7706.  
Negative Input of the Differential Analog Input Pair AIN1(+)/AIN1(−) for AD7705. COMMON input for  
AD7706 with Channel 1, Channel 2, and Channel 3 referenced to this input.  
9
REF IN(+)  
REF IN(−)  
REF IN(+)  
REF IN(−)  
Reference Input. Positive input of the differential reference input to the AD7705/AD7706. The reference  
input is differential with the provision that REF IN(+) must be greater than REF IN(−).  
REF IN(+) can lie anywhere between VDD and GND.  
Reference Input. Negative input of the differential reference input to the AD7705/AD7706. The  
REF IN(−) can lie anywhere between VDD and GND, provided that REF IN(+) is greater than REF IN(−).  
10  
11  
12  
AIN2(−)  
DRDY  
AIN3  
DRDY  
Negative Input of the Differential Analog Input Pair AIN2(+)/AIN2(−) for AD7705. Channel 3 for AD7706.  
Logic Output. A logic low on this output indicates that a new output word is available from the  
AD7705/AD7706 data register. The DRDY pin returns high upon completion of a read operation of a  
full output word. If no data read has taken place between output updates, the DRDY line returns high  
for 500 ꢀ tCLK IN cycles prior to the next output update. While DRDY is high, a read operation should  
neither be attempted nor in progress to avoid reading from the data register as it is being updated.  
The DRDY line returns low after the update has taken place. DRDY is also used to indicate when the  
AD7705/AD7706 has completed its on-chip calibration sequence.  
13  
DOUT  
DOUT  
Serial Data Output. Serial data is read from the output shift register on the part. The output shift  
register can contain information from the setup register, communication register, clock register, or  
data register, depending on the register selection bits of the communication register.  
Rev. C | Page 10 of 44  
 
1...78910111213...44

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