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AD7528KNZ

更新时间： 2024-01-22 22:21:33
品牌 Logo 应用领域
亚德诺 - ADI 光电二极管转换器
页数 文件大小 规格书
8页 210K
描述
CMOS Dual 8-Bit Buffered Multiplying DAC

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AD7528KNZ 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Not Recommended零件包装代码：DIP
包装说明：DIP, DIP20,.3针数：20
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：7.3
转换器类型：D/A CONVERTER输入位码：BINARY, OFFSET BINARY
输入格式：PARALLEL, 8 BITSJESD-30 代码：R-PDIP-T20
JESD-609代码：e3最大线性误差 (EL)：0.3906%
位数：8功能数量：1
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP20,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT APPLICABLE电源：5/15 V
认证状态：Not Qualified最大稳定时间：
子类别：Other Converters最大压摆率：2 mA
标称供电电压：5 V表面贴装：NO
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT APPLICABLE宽度：7.62 mm
Base Number Matches：1

AD7528KNZ 数据手册

 浏览型号AD7528KNZ的Datasheet PDF文件第1页浏览型号AD7528KNZ的Datasheet PDF文件第2页浏览型号AD7528KNZ的Datasheet PDF文件第3页浏览型号AD7528KNZ的Datasheet PDF文件第5页浏览型号AD7528KNZ的Datasheet PDF文件第6页浏览型号AD7528KNZ的Datasheet PDF文件第7页 
AD7528  
INTERFACE LOGIC INFORMATION  
DAC Selection:  
Both DAC latches share a common 8-bit input port. The con-  
trol input DAC A/DAC B selects which DAC can accept data  
from the input port.  
Figure 1. An inverted R-2R ladder structure is used, that is, bi-  
nary weighted currents are switched between the DAC output  
and AGND thus maintaining fixed currents in each ladder leg  
independent of switch state.  
EQUIVALENT CIRCUIT ANALYSIS  
Mode Selection:  
Inputs CS and WR control the operating mode of the selected  
DAC. See Mode Selection Table below.  
Figure 2 shows an approximate equivalent circuit for one of the  
AD7528’s D/A converters, in this case DAC A. A similar  
equivalent circuit can be drawn for DAC B. Note that AGND  
(Pin 1) is common for both DAC A and DAC B.  
Write Mode:  
When CS and WR are both low the selected DAC is in the write  
mode. The input data latches of the selected DAC are transpar-  
ent and its analog output responds to activity on DB0–DB7.  
The current source ILEAKAGE is composed of surface and junc-  
tion leakages and, as with most semiconductor devices, approxi-  
mately doubles every 10°C. The resistor RO as shown in Figure  
2 is the equivalent output resistance of the device which varies  
with input code (excluding all 0s code) from 0.8 R to 2 R. R is  
typically 11 kΩ. COUT is the capacitance due to the N-channel  
switches and varies from about 50 pF to 120 pF depending  
upon the digital input. g(VREF A, N) is the Thevenin equivalent  
voltage generator due to the reference input voltage VREF A and  
the transfer function of the R-2R ladder.  
Hold Mode:  
The selected DAC latch retains the data which was present on  
DB0–DB7 just prior to CS or WR assuming a high state. Both  
analog outputs remain at the values corresponding to the data in  
their respective latches.  
Mode Selection Table  
DAC A/DAC B  
CS  
WR  
DAC A  
DAC B  
L
H
X
L
L
H
L
L
X
WRITE  
HOLD  
HOLD  
HOLD  
WRITE  
HOLD  
R
R
A
R
O
FB  
OUT A  
g(V  
A, N)  
C
OUT  
I
REF  
X
X
H
HOLD  
HOLD  
LKG  
AGND  
L = Low State; H = High State; X = Don’t Care.  
Figure 2. Equivalent Analog Output Circuit of DAC A  
WRITE CYCLE TIMING DIAGRAM  
CIRCUIT INFORMATION–DIGITAL SECTION  
tCH  
tCS  
V
The input buffers are simple CMOS inverters designed such  
that when the AD7528 is operated with VDD = 5 V, the buffer  
converts TTL input levels (2.4 V and 0.8 V) into CMOS logic  
levels. When VIN is in the region of 2.0 volts to 3.5 volts the  
input buffers operate in their linear region and pass a quiescent  
current, see Figure 3. To minimize power supply currents it is  
recommended that the digital input voltages be as close to the  
supply rails (VDD and DGND) as is practically possible.  
DD  
CHIP SELECT  
0
tAH  
V
tAS  
DD  
DAC A/DAC B  
0
tWR  
V
DD  
WRITE  
0
tDS  
tDH  
V
0
DD  
V
V
DATA IN  
(DB0 – DB7)  
IH  
DATA IN STABLE  
The AD7528 may be operated with any supply voltage in the  
range 5 ≤ VDD ≤ 15 volts. With VDD = +15 V the input logic  
levels are CMOS compatible only, i.e., 1.5 V and 13.5 V.  
IL  
NOTES:  
1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED  
FROM 10% TO 90% OF V  
.
DD  
V
V
= +5V, t = t = 20ns;  
= +15V, t = t = 40ns;  
DD  
DD  
r f  
r
f
V
+ V  
2
9
IH  
IL  
2. TIMING MEASUREMENT REFERENCE LEVEL IS  
V
= +15V  
800  
700  
600  
500  
400  
300  
200  
100  
8
7
6
5
4
3
2
1
T
= +25؇C  
DD  
A
ALL DIGITAL INPUTS  
TIED TOGETHER  
CIRCUIT INFORMATION—D/A SECTION  
The AD7528 contains two identical 8-bit multiplying D/A con-  
verters, DAC A and DAC B. Each DAC consists of a highly  
stable thin film R-2R ladder and eight N-channel current steer-  
ing switches. A simplified D/A circuit for DAC A is shown in  
V
= +5V  
DD  
R
R
R
V
A
REF  
2R  
S1  
2R  
S2  
2R  
S3  
2R  
S8  
2R  
0
1
2
3
4
5
6
V
7
8
9
10 11 12 13 14  
R
R
A
– Volts  
FB  
IN  
OUT A  
AGND  
Figure 3. Typical Plots of Supply Current, IDD vs. Logic  
Input Voltage VIN, for VDD = +5 V and +15 V  
DAC A DATA LATCHES  
AND DRIVERS  
Figure 1. Simplified Functional Circuit for DAC A  
–4–  
REV. B  
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