AD7523, AD7533
Unipolar Binary Operation - AD7533 (10-Bit DAC)
3. To increase V
, connect a series resistor, R2, (0Ω to
OUT
250Ω) in the I
amplifier feedback loop.
OUT1
The circuit configuration for operating the AD7533 in
unipolar mode is shown in Figure 2. With positive and
4. To decrease V
OUT
, connect a series resistor, R1, (0Ω to
250Ω) between the reference voltage and the V
terminal.
negative V
values the circuit is capable of 2-Quadrant
REF
REF
multiplication. The “Digital Input Code/Analog Output Value”
table for unipolar mode is given in Table 2.
Bipolar (Offset Binary) Operation - AD7523
TABLE 2. UNlPOLAR BINARY CODE - AD7533
The circuit configuration for operating the AD7523 in the
bipolar mode is given in Figure 3. Using offset binary digital
input codes and positive and negative reference voltage
values, Four-Quadrant multiplication can be realized. The
“Digital Input Code/Analog Output Value” table for bipolar
mode is given in Table 3.)
DIGITAL INPUT
MSB LSB
(NOTE 1)
NOMINAL ANALOG OUTPUT
1023
1024
------------
1111111111
1000000001
–V
–V
REF
REF
513
------------
1024
A “Logic 1” input at any digital input forces the corresponding
ladder switch to steer the bit current to I
bus. A “Logic
OUT1
bus. For any code the
V
0” input forces the bit current to I
OUT2
bus currents are complements of one
512
------------
= –--------------
REF
2
1000000000
0111111111
0000000001
0000000000
–V
I
and I
REF
1024
OUT1
another. The current amplifier at I
OUT2
changes the polarity
OUT2
current and the transconductance amplifier at I
511
------------
–V
–V
of I
REF
REF
OUT2
OUT
1024
output sums the two currents. This configuration doubles the
output range. The difference current resulting at zero offset
binary code, (MSB = “Logic 1”, all other bits = “Logic 0”), is
1
------------
1024
0
corrected by suing an external resistor, (10MΩ), from V
------------
1024
REF
–V
= 0
REF
to I
(Figure 3).
OUT2
NOTES:
1. V
TABLE 3. BlPOLAR (OFFSET BINARY) CODE - AD7523
as shown in the Functional Diagram.
OUT
DIGITAL INPUT
2. Nominal Full Scale for the circuit of Figure 2 is given by:
MSB LSB
ANALOG OUTPUT
1023
1024
------------
FS = –V
.
REF
127
128
---------
11111111
–V
–V
REF
3. Nominal LSB magnitude for the circuit of Figure 2 is given by:
1
1
---------
128
10000001
10000000
01111111
00000001
00000000
REF
------------
LSB = V
.
REF
1024
0
Zero Offset Adjustment
1
---------
128
+V
+V
+V
1. Connect all digital inputs to GND.
REF
REF
REF
127
---------
128
2. Adjust the offset zero adjust trimpot of the output
operational amplifier for 0V ±1mV (Max) at V
.
OUT
128
---------
128
Gain Adjustment
1. Connect all digital inputs to V+.
10
NOTE:
–7
1
128
2. Monitor V
for a -V
(1 - 1/2 ) reading.
OUT
REF
---------
1. 1 LSB = (2 )(V
) =
(V
).
REF
REF
±10V +15V
REF
V
R1
R2
15
14
16
MSB
LSB
R
FEEDBACK
4
I
OUT1
DATA
INPUTS
AD7523/
AD7533
1
2
-
I
R4 5K
R3 5K
CR1
OUT2
V
OUT
6
+
13
3
R6 10MΩ
-
6
CR2
+
FIGURE 3. BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION)
10-12
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