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AD7478ARTZ-REEL73 PDF预览

AD7478ARTZ-REEL73

更新时间: 2024-09-30 12:35:39
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
24页 466K
描述
1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23

AD7478ARTZ-REEL73 数据手册

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1 MSPS, 12-/10-/8-Bit ADCs  
in 6-Lead SOT-23  
AD7476/AD7477/AD7478  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
V
Fast throughput rate: 1 MSPS  
Specified for VDD of 2.35 V to 5.25 V  
Low power  
DD  
12-/10-/8-BIT  
SUCCESSIVE-  
APPROXIMATION  
ADC  
V
3.6 mW at 1 MSPS with 3 V supplies  
15 mW at 1 MSPS with 5 V supplies  
Wide input bandwidth  
IN  
70 dB SNR at 100 kHz input frequency  
Flexible power/serial clock speed management  
No pipeline delays  
SCLK  
SDATA  
CS  
CONTROL  
LOGIC  
High speed serial interface  
AD7476/AD7477/AD7478  
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible  
Standby mode: 1 μA maximum  
6-lead SOT-23 package  
GND  
Figure 1.  
APPLICATIONS  
Battery-powered systems  
Personal digital assistants  
Medical instruments  
Mobile communications  
Instrumentation and control systems  
Data acquisition systems  
High speed modems  
Optical sensors  
GENERAL DESCRIPTION  
PRODUCT HIGHLIGHTS  
The AD7476/AD7477/AD74781 are, respectively, 12-bit, 10-bit,  
and 8-bit, high speed, low power, successive approximation  
ADCs. The parts operate from a single 2.35 V to 5.25 V power  
supply and feature throughput rates up to 1 MSPS. Each part  
contains a low noise, wide bandwidth track-and-hold amplifier  
that can handle input frequencies in excess of 6 MHz.  
1. First 12-/10-/8-Bit ADCs in SOT-23 Packages.  
2. High Throughput with Low Power Consumption.  
3. Flexible Power/Serial Clock Speed Management. The  
conversion rate is determined by the serial clock, allowing  
the conversion time to be reduced through the serial clock  
speed increase. This allows the average power consumption  
to be reduced while not converting. The parts also feature a  
shutdown mode to maximize power efficiency at lower  
throughput rates. Current consumption is 1 μA maximum  
when in shutdown mode.  
The conversion process and data acquisition are controlled  
CS  
using  
with microprocessors or DSPs. The input signal is sampled on  
CS  
and the serial clock, allowing the devices to interface  
the falling edge of  
and the conversion is initiated at this  
point. There are no pipeline delays associated with these parts.  
4. Reference Derived from the Power Supply.  
The AD7476/AD7477/AD7478 use advanced design techniques  
to achieve very low power dissipation at high throughput rates.  
The reference for the parts is taken internally from VDD. This  
allows the widest dynamic input range to the ADC. Thus, the  
analog input range for the parts are 0 V to VDD. The conversion  
rate is determined by the SCLK.  
5. No Pipeline Delay. The parts feature a standard successive-  
approximation ADC with accurate control of the sampling  
CS  
instant via a  
input and once-off conversion control.  
1 Protected by U.S. Patent No. 6,681,332.  
Rev. F  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 www.analog.com  
Fax: 781.461.3113 ©2000–2009 Analog Devices, Inc. All rights reserved.  
 
 

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