AD7352YRUZ

更新时间： 2024-02-11 08:17:07

品牌	Logo	应用领域
亚德诺 - ADI		转换器模数转换器光电二极管
页数	文件大小	规格书
20页	498K
描述
Differential Input, Dual, Simultaneous Sampling, 3 MSPS, 12-Bit, SAR ADC

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AD7352YRUZ 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	TSSOP
包装说明：	TSSOP, TSSOP16,.25	针数：	16
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.28
Is Samacsys：	N	转换器类型：	ADC, SUCCESSIVE APPROXIMATION
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e3
长度：	5 mm	最大线性误差 (EL)：	0.0244%
湿度敏感等级：	1	模拟输入通道数量：	1
位数：	12	功能数量：	2
端子数量：	16	最高工作温度：	125 °C
最低工作温度：	-40 °C	输出位码：	BINARY
输出格式：	SERIAL	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装等效代码：	TSSOP16,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	电源：	2.5 V
认证状态：	Not Qualified	采样速率：	3 MHz
采样并保持/跟踪并保持：	TRACK	座面最大高度：	1.2 mm
子类别：	Analog to Digital Converters	标称供电电压：	2.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	AUTOMOTIVE	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	4.4 mm	Base Number Matches：	1

AD7352YRUZ 数据手册

AD7352

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DRIVE

INA+

SCLK

SDATA

DGND

AGND

INA–

REF

AD7352

TOP VIEW

REFGND

AGND

(Not to Scale)

REF

INB–

INB+

Figure 2. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

Analog Inputs of ADC A. These analog inputs form a fully differential pair.

1, 2

3, 6

V_INA+, V_INA−

REF_A, REF_B

Reference Decoupling Capacitor Pins. Decoupling capacitors are connected between these pins and the

REFGND pin to decouple the reference buffer for each respective ADC. It is recommended to decouple each

reference pin with a 10 μF capacitor. Provided the output is buffered, the on-chip reference can be taken from

these pins and applied externally to the rest of the system. The nominal internal reference voltage is 2.048 V

and appears at these pins. These pins can also be overdriven by an external reference. The input voltage range

for the external reference is 2.048 V + 100 mV to V_DD

REFGND

AGND

Reference Ground. This is the ground reference point for the reference circuitry on the AD7352. Any external

reference signal should be referred to this REFGND voltage. Decoupling capacitors must be placed between

this pin and the REF_Aand REF_Bpins. Connect the REFGND pin to the AGND plane of a system.

Analog Ground. This is the ground reference point for all analog circuitry on the AD7352. Refer all analog input

signals to this AGND voltage. The AGND and DGND voltages should ideally be at the same potential and must

not be more than 0.3 V apart, even on a transient basis.

5, 11

7, 8

V_INB−, V_INB+

V_DD

Analog Inputs of ADC B. These analog inputs form a fully differential pair.

Power Supply Input. The V_DDrange for the AD7352 is 2.5 V 10%. Decouple the supply to AGND with a 0.1 ꢀF

capacitor in parallel with a 10 ꢀF tantalum capacitor.

Chip Select. Active low, logic input. This input provides the dual functions of initiating conversions on the

AD7352 and framing the serial data transfer.

Digital Ground. This is the ground reference point for all digital circuitry on the AD7352. Connect this pin to

the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must

not be more than 0.3 V apart, even on a transient basis.

DGND

13, 14

SDATA_B, SDATA_ASerial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on

the falling edge of the SCLK input. To access the 12 bits of data from the AD7352, 14 SCLK falling edges are

required. The data simultaneously appears on both data output pins from the simultaneous conversions of

both ADCs. The data stream consists of two leading zeros followed by 12 bits of conversion data. The data is

provided MSB first. If CS is held low for 16 SCLK cycles rather than 14 on the AD7352, then two trailing zeros

appear after the 12 bits of data. If CS is held low for a further 16 SCLK cycles on either SDATA_Aor SDATA_B, the

data from the other ADC follows on the SDATA pins. This allows data from a simultaneous conversion on both

ADCs to be gathered in serial format on either SDATA_Aor SDATA_B.

SCLK

Serial Clock, Logic Input. A serial clock input provides the serial clock for accessing the data from the AD7352.

This clock is also used as the clock source for the conversion process.

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates.

The voltage at this pin may be different than the voltage at V_DD. The V_DRIVEsupply should be decoupled to

DGND with a 0.1 ꢀF capacitor in parallel with a 10 ꢀF tantalum capacitor.

V_DRIVE

Rev. 0 | Page 7 of 20

1...4 5 678 9 10...20

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