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AD7280ABSTZ

更新时间： 2024-02-13 04:22:57
品牌 Logo 应用领域
亚德诺 - ADI 电池监控
页数 文件大小 规格书
48页 869K
描述
Lithium Ion Battery Monitoring System Cell balancing interface

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AD7280ABSTZ 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFP包装说明：LEAD FREE, MS-026BBC, LQFP-48
针数：48Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.82可调阈值：YES
模拟集成电路 - 其他类型：POWER SUPPLY SUPPORT CIRCUITJESD-30 代码：S-PQFP-G48
长度：9 mm信道数量：6
功能数量：1端子数量：48
最高工作温度：105 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装等效代码：QFP48,.35SQ,20封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH电源：7.5/30 V
认证状态：Not Qualified座面最大高度：1.6 mm
子类别：Power Management Circuits最大供电电流 (Isup)：10 mA
最大供电电压 (Vsup)：30 V最小供电电压 (Vsup)：7.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
宽度：9 mmBase Number Matches：1

AD7280ABSTZ 数据手册

 浏览型号AD7280ABSTZ的Datasheet PDF文件第5页浏览型号AD7280ABSTZ的Datasheet PDF文件第6页浏览型号AD7280ABSTZ的Datasheet PDF文件第7页浏览型号AD7280ABSTZ的Datasheet PDF文件第9页浏览型号AD7280ABSTZ的Datasheet PDF文件第10页浏览型号AD7280ABSTZ的Datasheet PDF文件第11页 
AD7280A  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
48 47 46 45 44 43 42 41 40 39 38 37  
1
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
VIN6  
AUX3  
AUX4  
AUX5  
AUX6  
PIN 1  
2
3
CB6  
VIN5  
CB5  
VIN4  
CB4  
VIN3  
CB3  
VIN2  
CB2  
VIN1  
CB1  
4
5
AUX  
TERM  
AD7280A  
TOP VIEW  
(Not to Scale)  
6
AGND  
7
AV  
CC  
8
V
DRIVE  
9
ALERTlo  
ALERT  
SDO  
10  
11  
12  
SDOlo  
13 14 15 16  
18  
20 21  
17  
19  
22 24  
23  
Figure 3. Pin Configuration  
Table 6. Pin Function Descriptions  
Pin No. Mnemonic Description  
1, 3, 5, 7, ±, VIN6 to VIN0  
11, 13  
Analog Input 6 to Analog Input 0. VIN0 should be connected to the base of the series-connected battery cells.  
VIN1 should be connected to the top of Cell 1, VIN2 should be connected to the top of Cell 2, and so on (see  
Figure 28 and Figure 2±).  
2, 4, 6, 8,  
10, 12  
CB6 to CB1  
MASTER  
Cell Balance Output 6 to Cell Balance Output 1. These pins provide a voltage output that can be used to supply  
the gate drive of an external cell balancing transistor. Each CBx output provides a 0 V or 5 V voltage output  
referenced to the absolute amplitude of the negative terminal of the battery cell that is being balanced.  
Voltage Input. Connect the MASTER pin of the AD7280A that is connected directly to the DSP/microprocessor  
to the VDD supply pin through a 10 kΩ resistor. In an application with two or more AD7280As in a daisy chain,  
the MASTER pins of the remaining AD7280As in the daisy chain should be tied to their respective VSS supply  
pins through 10 kΩ resistors.  
14  
15  
PD  
Power-Down Input. This input is used to power down the AD7280A. When the AD7280A acts as a master, the  
PD input is supplied from the DSP/microprocessor. When the AD7280A acts as a slave in a daisy chain, the  
PD input should be connected to the PDhi output of the AD7280A immediately below it in potential in the  
daisy chain.  
16  
VDD  
Positive Power Supply Voltage for the High Voltage Analog Input Structure of the AD7280A. The supply must be  
greater than the minimum voltage of 8 V. VDD can be supplied directly from the cell with the highest potential  
of the four, five, or six cell battery stacks that the AD7280A is monitoring. The maximum voltage that should  
be applied between VDD and VSS is 30 V. Place 10 μF and 100 nF decoupling capacitors on the VDD pin.  
17  
18  
VSS  
Negative Power Supply Voltage for the High Voltage Analog Input Structure of the AD7280A. This input should  
be at the same potential as the AGND/DGND voltage.  
Analog Voltage Output, 5.2 V. The internally generated VREG voltage, which provides the supply voltage for  
the ADC core, is available on this pin for use external to the AD7280A. Place 1 μF and 100 nF decoupling  
capacitors on the VREG pin.  
VREG  
1±  
20  
DVCC  
Digital Supply Voltage, 4.± V to 5.5 V. The DVCC and AVCC voltages should ideally be at the same potential.  
For best performance, it is recommended that the DVCC and AVCC pins be shorted together to ensure that  
the voltage difference between them never exceeds 0.3 V, even on a transient basis. This supply should be  
decoupled to DGND. Place 100 nF decoupling capacitors on the DVCC pin. The DVCC supply pin should be  
connected to the VREG output.  
DGND  
Digital Ground. Ground reference point for all digital circuitry on the AD7280A. The DGND and AGND voltages  
should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.  
Rev. 0 | Page 8 of 48  
 
 
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