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AD7280ABSTZ

更新时间： 2024-02-23 07:42:44
品牌 Logo 应用领域
亚德诺 - ADI 电池监控
页数 文件大小 规格书
48页 869K
描述
Lithium Ion Battery Monitoring System Cell balancing interface

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AD7280ABSTZ 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFP包装说明：LEAD FREE, MS-026BBC, LQFP-48
针数：48Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.82可调阈值：YES
模拟集成电路 - 其他类型：POWER SUPPLY SUPPORT CIRCUITJESD-30 代码：S-PQFP-G48
长度：9 mm信道数量：6
功能数量：1端子数量：48
最高工作温度：105 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装等效代码：QFP48,.35SQ,20封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH电源：7.5/30 V
认证状态：Not Qualified座面最大高度：1.6 mm
子类别：Power Management Circuits最大供电电流 (Isup)：10 mA
最大供电电压 (Vsup)：30 V最小供电电压 (Vsup)：7.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
宽度：9 mmBase Number Matches：1

AD7280ABSTZ 数据手册

 浏览型号AD7280ABSTZ的Datasheet PDF文件第3页浏览型号AD7280ABSTZ的Datasheet PDF文件第4页浏览型号AD7280ABSTZ的Datasheet PDF文件第5页浏览型号AD7280ABSTZ的Datasheet PDF文件第7页浏览型号AD7280ABSTZ的Datasheet PDF文件第8页浏览型号AD7280ABSTZ的Datasheet PDF文件第9页 
AD7280A  
TIMING SPECIFICATIONS  
VDD = 8 V to 30 V, VSS = 0 V, DVCC = AVCC = VREG, VDRIVE = 2.7 V to 5.5 V, TA = −40°C to +105°C, unless otherwise noted.  
Table 3.  
Parameter1  
Min  
Typ  
Max  
Unit  
Description  
tCONV  
ADC conversion time  
425  
425  
560  
6±5  
720  
ns  
ns  
−40°C to +85°C  
−40°C to +105°C  
tACQ  
tACQ  
tACQ  
tACQ  
ADC acquisition time, Bits[D6:D5] of the control register set to 00  
−40°C to +85°C  
−40°C to +105°C  
ADC acquisition time, Bits[D6:D5] of the control register set to 01  
−40°C to +85°C  
−40°C to +105°C  
ADC acquisition time, Bits[D6:D5] of the control register set to 10  
−40°C to +85°C  
340  
340  
400  
465  
470  
ns  
ns  
665  
665  
800  
1010  
1030  
ns  
ns  
1005  
1005  
1200  
1460  
1510  
ns  
ns  
−40°C to +105°C  
ADC acquisition time, Bits[D6:D5] of the control register set to 11  
−40°C to +85°C  
1340  
1340  
1600  
200  
18±0  
1±45  
250  
ns  
ns  
ns  
−40°C to +105°C  
tDELAY  
tWAIT  
Propagation delay between the falling edges of CNVST of adjacent  
parts in the daisy chain  
Time required between the end of conversions and the beginning  
of readback of the conversion results  
5
ꢀs  
fSCLK  
tQUIET  
1
MHz  
ns  
Frequency of serial read clock  
Minimum quiet time required between the end of a serial read and  
the start of the next conversion  
200  
2
t1  
0.4  
10  
50  
20  
μs  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
μs  
CNVST low pulse  
t2  
t3  
t4  
t5  
CS falling edge to SCLK rising edge  
Delay from CS falling edge until SDO is three-state disabled  
SDI setup time prior to SCLK falling edge  
SDI hold time after SCLK falling edge  
Data access time after SCLK rising edge  
SCLK to data valid hold time  
SCLK high pulse width  
SCLK low pulse width  
CS rising edge to SCLK rising edge  
CS rising edge to SDO high impedance  
CS high time required between each 32-bit write/read command  
5
4
3
t6  
28  
10  
t7  
t8  
t±  
20  
0.45 × tSCLK  
0.45 × tSCLK  
100  
4
t10  
t11  
t12  
3
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to ±0% of VDRIVE) and timed from a voltage level of 1.6 V.  
All timing specifications given are with a 25 pF load capacitance.  
2
CNVST  
CNVST  
pin is not gated.  
Maximum allowed  
low pulse time to ensure that a software power-down state is not entered when the  
3 Time required for the output to cross 0.4 V or 2.4 V.  
4 t10 applies when using a continuous SCLK. Guaranteed by design.  
Timing Diagram  
CS  
t12  
t8  
t10  
32  
t2  
1
2
3
4
SCLK  
SDO  
SDI  
t7  
t9  
t11  
t3  
t6  
MSB  
MSB – 1  
t5  
LSB  
THREE-STATE  
THREE-STATE  
t4  
MSB  
MSB – 1  
LSB  
Figure 2. Serial Interface Timing Diagram  
Rev. 0 | Page 6 of 48  
 
 
 
 
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