AD7278ARMZ

更新时间： 2024-02-17 05:28:03

品牌	Logo	应用领域
亚德诺 - ADI		转换器模数转换器光电二极管 PC
页数	文件大小	规格书
28页	501K
描述
3 MSPS, 12-/10-/8-Bit ADCs in 6-Lead TSOT

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技术参数
数据手册

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AD7278ARMZ 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	TSSOP
包装说明：	TSSOP,	针数：	8
Reach Compliance Code：	unknown	风险等级：	5.68
Is Samacsys：	N	最大模拟输入电压：	3.6 V
最小模拟输入电压：		最长转换时间：	0.291 µs
转换器类型：	ADC, SUCCESSIVE APPROXIMATION	JESD-30 代码：	S-PDSO-G8
JESD-609代码：	e3	长度：	3 mm
最大线性误差 (EL)：	0.3906%	湿度敏感等级：	1
模拟输入通道数量：	1	位数：	8
功能数量：	1	端子数量：	8
最高工作温度：	125 °C	最低工作温度：	-40 °C
输出位码：	BINARY	输出格式：	SERIAL
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装形状：	SQUARE	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	采样速率：	3 MHz
采样并保持/跟踪并保持：	TRACK	座面最大高度：	1.1 mm
标称供电电压：	3 V	表面贴装：	YES
温度等级：	AUTOMOTIVE	端子面层：	MATTE TIN
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	40
宽度：	3 mm	Base Number Matches：	1

AD7278ARMZ 数据手册

AD7276/AD7277/AD7278

SERIAL INTERFACE

Figure 31 through Figure 34 show the detailed timing diagrams

for serial interfacing to the AD7276, AD7277, and AD7278. The

serial clock provides the conversion clock and controls the transfer

of information from the AD7276/AD7277/AD7278 during

conversion.

If 16 SCLKs are considered in the cycle, then the AD7278 clocks

out six trailing zeros for the last six bits and SDATA returns to

three-state on the 16^thSCLK falling edge, as shown in Figure 34.

If the user considers a 14 SCLK cycle serial interface for the

AD7276/AD7277/AD7278, then

must be brought high after

the 14^thSCLK falling edge. Then the last two trailing zeros are

ignored, and SDATA goes back into three-state. In this case, the

3 MSPS throughput can be achieved by using a 48 MHz clock

frequency.

The

signal initiates the data transfer and conversion process.

The falling edge of

and takes the bus out of three-state. The analog input is sampled

and the conversion is initiated at this point.

puts the track-and-hold into hold mode

going low clocks out the first leading zero to be read by the

For the AD7276, the conversion requires completing 14 SCLK

cycles. Once 13 SCLK falling edges have elapsed, the track-and-

hold goes back into track mode on the next SCLK rising edge,

microcontroller or DSP. The remaining data is then clocked out

by subsequent SCLK falling edges, beginning with the second

leading zero. Therefore, the first falling clock edge on the serial

clock provides the first leading zero and clocks out the second

leading zero. The final bit in the data transfer is valid on the 16^th

falling edge, because it is clocked out on the previous (15^th)

falling edge.

as shown in Figure 31 at Point B. If the rising edge of

occurs

before 14 SCLKs have elapsed, the conversion is terminated and

the SDATA line goes back into three-state. If 16 SCLKs are

considered in the cycle, the last two bits are zeros and SDATA

returns to three-state on the 16^thSCLK falling edge, as shown in

Figure 32.

In applications with a slower SCLK, it is possible to read data on

each SCLK rising edge. In such cases, the first falling edge of SCLK

clocks out the second leading zero and can be read on the first

rising edge. However, the first leading zero clocked out when

goes low is missed if read within the first falling edge. The

15^thfalling edge of SCLK clocks out the last bit and can be read

on the 15^thrising SCLK edge.

For the AD7277, the conversion requires completing 12 SCLK

cycles. Once 11 SCLK falling edges elapse, the track-and-hold

goes back into track mode on the next SCLK rising edge, as

shown in Figure 33 at Point B. If the rising edge of

occurs

before 12 SCLKs elapse, the conversion is terminated and the

SDATA line goes back into three-state. If 16 SCLKs are considered

in the cycle, the AD7277 clocks out four trailing zeros for the

last four bits and SDATA returns to three-state on the 16^thSCLK

falling edge, as shown in Figure 33.

goes low just after one SCLK falling edge elapses, then

clocks out the first leading zero and can be read on the SCLK

rising edge. The next SCLK falling edge clocks out the second

leading zero and can be read on the following rising edge.

For the AD7278, the conversion requires completing 10 SCLK

cycles. Once 9 SCLK falling edges elapse, the track-and-hold

goes back into track mode on the next rising edge. If the rising

edge of

occurs before 10 SCLKs elapse, the part enters power-

down mode.

t₁

t_CONVERT

t₆

t₂

SCLK

t₅

t₉

t₇

t₃

t_QUIET

t₄

DB9

ZERO

DB11

DB10

DB1

DB0

SDATA

THREE-STATE

THREE-

STATE

2 LEADING

ZEROS

1/THROUGHPUT

Figure 31. AD7276 Serial Interface Timing Diagram 14 SCLK Cycle

Rev. C | Page 22 of 28

1...19 20 212223 24 25...28

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与AD7278ARMZ相关器件

型号	品牌	描述	获取价格	数据表
AD7278ARMZ-RL	ADI	3 MSPS, 12-/10-/8-Bit ADCs in 6-Lead TSOT	获取价格
AD7278AUJZ-500RL7	ADI	3 MSPS, 12-/10-/8-Bit ADCs in 6-Lead TSOT	获取价格
AD7278AUJZ-RL7	ADI	3 MSPS, 12-/10-/8-Bit ADCs in 6-Lead TSOT	获取价格
AD7278BRMJ	ADI	3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT	获取价格
AD7278BRMZ	ADI	3 MSPS, 12-/10-/8-Bit ADCs in 6-Lead TSOT	获取价格
AD7278BRMZ-REEL	ADI	3 MSPS, 12-/10-/8-Bit ADCs in 6-Lead TSOT	获取价格

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