AD7265BSUZ

更新时间： 2024-01-04 09:39:41

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
28页	690K
描述
Differential/Single-Ended Input, Dual 1 MSPS, 12-Bit, 3-Channel SAR ADC

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AD7265BSUZ 数据手册

AD7265

Pin No. Mnemonic

Description

28, 30

D_OUTB, D_OUT

Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on

the falling edge of the SCLK input and 14 SCLKs are required to access the data. The data simultaneously appears

on both pins from the simultaneous conversions of both ADCs. The data stream consists of two leading zeros

followed by the 12 bits of conversion data. The data is provided MSB first. If CS is held low for 16 SCLK cycles

rather than 14, then two trailing zeros appear after the 12 bits of data. If CS is held low for a further 16 SCLK

cycles on either D_OUTA or D_OUTB, the data from the other ADC follows on the D_OUTpin. This allows data from a

simultaneous conversion on both ADCs to be gathered in serial format on either D_OUTA or D_OUTB using only one

serial port. See the Serial Interface section.

V_DRIVE

DV_DD

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates.

This pin should be decoupled to DGND. The voltage at this pin may be different than that at AV_DDand DV_DDbut

should never exceed either by more than 0.3 V.

Digital Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for all digital circuitry on the AD7265. The DV_DD

and AV_DDvoltages should ideally be at the same potential and must not be more than 0.3 V apart even on a

transient basis. This supply should be decoupled to DGND.

Rev. A | Page 8 of 28

1...5 6 789 10 11...28

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型号	品牌	描述	获取价格	数据表
AD7265BSUZ-REEL	ADI	Differential/Single-Ended Input, Dual 1 MSPS, 12-Bit, 3-Channel SAR ADC	获取价格
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AD7266ASU	ADI	Differential Input, Dual 2 MSPS, 12-Bit, 3-Channel SAR ADC	获取价格
AD7266BCP	ADI	Differential Input, Dual 2 MSPS, 12-Bit, 3-Channel SAR ADC	获取价格