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AD7265BSUZ PDF预览

AD7265BSUZ

更新时间: 2024-02-21 23:58:54
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
28页 690K
描述
Differential/Single-Ended Input, Dual 1 MSPS, 12-Bit, 3-Channel SAR ADC

AD7265BSUZ 数据手册

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AD7265  
Parameter  
Specification  
Unit  
Test Conditions/Comments  
DC Leakage Current  
Input Capacitance  
1
45  
10  
μA max  
pF typ  
pF typ  
When in track  
When in hold  
REFERENCE INPUT/OUTPUT  
Reference Output Voltage8  
Long-Term Stability  
Output Voltage Hysteresis2  
Reference Input Voltage Range  
DC Leakage Current  
2.5  
150  
50  
0.1/VDD  
2
V min/V max  
ppm typ  
ppm typ  
V min/V max  
μA max  
0.2ꢀ max @ 25ꢁC  
For 1000 hours  
See Typical Performance Characteristics section  
External reference applied to Pin DCAPA/Pin DCAP  
B
Input Capacitance  
25  
pF typ  
DCAPA, DCAPB Output Impedance  
Reference Temperature Coefficient  
10  
20  
10  
20  
Ω typ  
ppm/ꢁC max  
ppm/ꢁC typ  
μV rms typ  
VREF Noise  
LOGIC INPUTS  
Input High Voltage, VINH  
Input Low Voltage, VINL  
Input Current, IIN  
2.8  
0.4  
15  
5
V min  
V max  
nA typ  
pF typ  
VIN = 0 V or VDRIVE  
3
Input Capacitance, CIN  
LOGIC OUTPUTS  
Output High Voltage, VOH  
Output Low Voltage, VOL  
Floating State Leakage Current  
Floating State Output Capacitance3  
Output Coding  
VDRIVE − 0.2  
0.4  
1
V min  
V max  
μA max  
pF typ  
7
SGL/DIFF = 1 with 0 V to VREF range selected  
Straight (natural) binary  
Twos complement  
SGL/DIFF = 0; SGL/DIFF = 1 with 0 V to 2 × VREF range  
CONVERSION RATE  
Conversion Time  
14  
90  
110  
1
SCLK cycles  
ns max  
ns max  
MSPS max  
875 ns with SCLK = 16 MHz  
Full-scale step input; VDD = 5 V  
Full-scale step input; VDD = 3 V  
Track-and-Hold Acquisition Time3  
Throughput Rate  
POWER REQUIREMENTS  
VDD  
2.7/5.25  
2.7/5.25  
V min/V max  
V min/V max  
VDRIVE  
IDD  
Digital I/Ps = 0 V or VDRIVE  
VDD = 5.25 V  
VDD = 5.25 V; 3.5 mA typ  
VDD = 3.6 V; 2.7 mA typ  
Static  
Normal Mode (Static)  
Operational, fS = 1 MSPS  
fS = 1 MSPS  
Partial Power-Down Mode  
Full Power-Down Mode (VDD)  
2.3  
4
3.2  
500  
1
mA max  
mA max  
mA max  
μA max  
μA max  
μA max  
TA = −40ꢁC to +85ꢁC  
TA > 85ꢁC to 125ꢁC  
2.8  
Power Dissipation  
Normal Mode (Operational)  
Partial Power-Down (Static)  
Full Power-Down (Static)  
21  
2.625  
5.25  
mW max  
mW max  
μW max  
VDD = 5.25 V  
VDD = 5.25 V  
VDD = 5.25 V, TA = −40ꢁC to +85ꢁC  
1 Temperature range is −40ꢁC to +125ꢁC.  
2 See Terminology section.  
3 Sample tested during initial release to ensure compliance.  
4 Guaranteed no missed codes to 12 bits.  
5 VINor VIN+ must remain within GND/VDD  
.
6 VIN− = 0 V for specified performance. For full input range on VIN− pin, see Figure 28 and Figure 29.  
7 For full common-mode range, see Figure 24 and Figure 25.  
8 Relates to Pin DCAPA or Pin DCAPB.  
Rev. A | Page 4 of 28  
 

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