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AD7228ABR-REEL PDF预览

AD7228ABR-REEL

更新时间: 2024-01-29 20:20:23
品牌 Logo 应用领域
亚德诺 - ADI 输入元件信息通信管理光电二极管转换器
页数 文件大小 规格书
8页 206K
描述
IC OCTAL, PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, PDSO24, SOIC-24, Digital to Analog Converter

AD7228ABR-REEL 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOIC-24针数:24
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.31
最大模拟输出电压:5 V最小模拟输出电压:-5 V
转换器类型:D/A CONVERTER输入位码:BINARY
输入格式:PARALLEL, 8 BITSJESD-30 代码:R-PDSO-G24
JESD-609代码:e0长度:15.4 mm
最大线性误差 (EL):0.391%湿度敏感等级:3
标称负供电电压:-5 V位数:8
功能数量:8端子数量:24
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP24,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):240
电源:5/15,GND/-5 V认证状态:Not Qualified
座面最大高度:2.65 mm最大稳定时间:5 µs
子类别:Other Converters最大压摆率:20 mA
标称供电电压:15 V表面贴装:YES
技术:BICMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.5 mm
Base Number Matches:1

AD7228ABR-REEL 数据手册

 浏览型号AD7228ABR-REEL的Datasheet PDF文件第2页浏览型号AD7228ABR-REEL的Datasheet PDF文件第3页浏览型号AD7228ABR-REEL的Datasheet PDF文件第4页浏览型号AD7228ABR-REEL的Datasheet PDF文件第5页浏览型号AD7228ABR-REEL的Datasheet PDF文件第6页浏览型号AD7228ABR-REEL的Datasheet PDF文件第8页 
AD7228A  
DACs for correct timing relationships during the calibration  
cycle of the instrument.  
Figure 12. Self-Program m able Reference  
Figure 10b. AD7228A Tim ing Deskew Circuit  
CO ARSE/FINE AD JUST  
T he DACs on the AD7228A can be paired together to form a  
coarse/fine adjust function as indicated in Figure 11. T he func-  
tion is achieved using one external op amp and a few resistors  
per pair of DACs.  
DAC1 is the most significant or coarse DAC. Data is first  
loaded to this DAC to coarsely set the output voltage. DAC2 is  
then used to fine tune this output voltage. Varying the ratio of  
R1 to R2 varies the relative effect of the coarse and fine DACs  
on the output voltage. For the resistor values shown, DAC2 has  
a resolution of 150 µV in a 10 V output range. Since each DAC  
on the AD7228A is guaranteed monotonic, the coarse adjust-  
ment and fine adjustment are each monotonic. One application  
for this is as a set-point controller (see “Circuit Applications of  
the AD7226 Quad CMOS DAC” available from Analog Devices,  
Publication Number E873–15–11/84).  
Figure 13. Variation of VREF with Feedback Configuration  
MICRO P RO CESSO R INTERFACING  
Figure 14. AD7228A to 8085A/Z80 Interface  
Figure 11. Coarse/Fine Adjust Circuit  
SELF-P RO GRAMMABLE REFERENCE  
T he circuit of Figure 12 shows how one DAC of the AD7228,  
in this case DAC1, may be used in a feedback configuration to  
provide a programmable reference for itself and the other seven  
converters. T he relationship of VREF to VIN is expressed by  
1 + G  
(
)
VREF  
=
VIN  
where G = R2/R1  
1 + G D  
(
)
1
Figure 13 shows typical plots of VREF versus digital code, D1, for  
three different values of G. With VIN = 2.5 V and G = 3 the  
voltage at the output varies between 2.5 V and 10 V giving an  
effective 10-bit dynamic range to the other seven converters. For  
correct operation of the circuit, VSS should be –5 V and R1  
greater than 6.8 k.  
Figure 15. AD7228A to 6809/6502 Interface  
–7–  
REV. A  

AD7228ABR-REEL 替代型号

型号 品牌 替代类型 描述 数据表
AD7228KRZ-REEL ADI

完全替代

OCTAL, PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, PDSO24, SOIC-24
AD7228ABRZ-REEL ADI

完全替代

LC2MOS Octal 8-Bit DAC

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