AD7228A–SPECIFICATIONS
1
(V = 10.8 V to 16.5 V; V = –5 V ؎ 10%; GND = 0 V; V = +2 V to +10 V ; R = 2 kΩ, C = 100 pF unless otherwise
DD
SS
REF
L
L
noted.) All specifications TMIN to TMAX unless otherwise noted.
DUAL SUPPLY
B
C
T
U
P aram eter
Version2
Version
Version
Version
Units
Conditions/Com m ents
ST AT IC PERFORMANCE
Resolution
8
8
±1
±1/2
±1
8
8
±1
±1/2
±1
Bits
T otal Unadjusted Error3
Relative Accuracy
Differential Nonlinearity
Full-Scale Error4
±2
±1
±1
±1
±2
±1
±1
±1
LSB max
LSB max
LSB max
LSB max
VDD = +15 V ± 10%, VREF = +10 V
Guaranteed Monotonic
T ypical tempco is 5 ppm/°C with VREF = +10 V
±1/2
±1/2
Zero Code Error
@ 25°C
T MIN to T MAX
Minimum Load Resistance
±25
±30
2
±15
±20
2
±25
±30
2
±15
±20
2
mV max
mV max
kΩ min
T ypical tempco is 30 µV/°C
VOUT = +10 V
REFERENCE INPUT
Voltage Range1
Input Resistance
Input Capacitance5
AC Feedthrough
2 to 10
2
500
–70
2 to 10
2
500
–70
2 to 10
2
500
–70
2 to 10
2
500
–7 0
V min/V max
kΩ min
pF max
Occurs when each DAC is loaded with all 1s.
VREF = 8 V p-p Sine Wave @ 10 kHz
dB typ
DIGIT AL INPUT S
Input High Voltage, VINH
Input Low Voltage, VINL
Input Leakage Current
Input Capacitance5
Input Coding
2.4
0.8
±1
2.4
0.8
±1
2.4
0.8
±1
2.4
0.8
±1
V min
V max
µA max
pF max
VIN = 0 V or VDD
8
8
8
8
Binary
Binary
Binary
Binary
DYNAMIC PERFORMANCE5
Voltage Output Slew Rate
Voltage Output Settling T ime
Positive Full-Scale Change
Negative Full-Scale Change
Digital Feedthrough
2
2
2
2
V/µs min
5
5
50
50
5
5
50
50
5
5
50
50
5
5
50
50
µs max
µs max
nV secs typ
nV secs typ
VREF = +10 V; Settling T ime to ±1/2 LSB
VREF = +10 V; Settling T ime to ±1/2 LSB
Code transition all 0s to all 1s. VREF = 0 V; WR = VDD
Code transition all 0s to all 1s. VREF = +10 V; WR = 0 V
Digital Crosstalk6
POWER SUPPLIES
VDD Range
VSS Range
IDD
10.8/16.5
–4.5/–5.5
10.8/16.5 10.8/16.5 10.8/16.5
–4.5/–5.5 –4.5/–5.5 –4.5/–5.5
V min/V max
V min/V max
For Specified Performance
For Specified Performance
Outputs Unloaded; VIN = VINL or VINH
@ 25°C
T MIN to T MAX
16
20
16
20
16
22
16
22
mA max
mA max
ISS
Outputs Unloaded; VIN = VINL or VINH
@ 25°C
T MIN to T MAX
14
18
14
18
14
20
14
20
mA max
mA max
(V = +15 V ؎ 10%, V ; = GND = 0 V; V = +10 V, R = 2 kΩ, C = 100 pF unless otherwise noted.)
DD
SS
REF
L
L
SINGLE SUPPLY
AII specifications TMIN to TMAX unless otherwise noted.
ST AT IC PERFORMANCE
Resolution
8
8
8
8
Bits
T otal Unadjusted Error3
Differential Nonlinearity
Minimum Load Resistance
±2
±1
2
±1
±1
2
±2
±1
2
±1
±1
2
LSB max
LSB max
kΩ min
Guaranteed Monotonic
VOUT = +10 V
REFERENCE INPUT
Input Resistance
2
500
2
500
2
500
2
500
kΩ min
pF max
Input Capacitance5
Occurs when each DAC is loaded with all 1s.
DIGIT AL INPUT S
As per Dual Supply Specifications
DYNAMIC PERFORMANCE5
Voltage Output Slew Rate
Voltage Output Settling T ime
Positive Full-Scale Change
Negative Full-Scale Change
Digital Feedthrough
2
2
2
2
V/µs min
5
7
50
50
5
7
50
50
5
7
50
50
5
7
50
50
µs max
µs max
nV secs typ
nV secs typ
Settling T ime to ±1/2 LSB
Settling T ime to ±1/2 LSB
Code transition all 0s to all 1s. VREF = 0 V; WR = VDD
Code transition all 0s to all 1s. VREF = +10 V, WR = 0 V
Digital Crosstalk6
POWER SUPPLIES
VDD Range
IDD
13.5/16.5
13.5/16.5 13.5/16.5 13.5/16.5
V min/V max
For Specified Performance
Outputs Unloaded; VIN = VINL or VINH
@ 25°C
T MIN to T MAX
16
20
16
20
16
22
16
22
mA max
mA max
NOT ES
1VOUT must be less than VDD by 3.5 V to ensure correct operation.
5Sample tested at 25°C to ensure compliance.
2T emperature ranges are as follows:
6T he glitch impulse transferred to the output of one converter (not addressed) due to a
change in the digital input code to another addressed converter.
B, C Versions; –40°C to +85°C
T , U Versions; –55°C to +125°C
3T otal Unadjusted Error includes zero code error, relative accuracy and full-scale error.
4Calculated after zero code error has been adjusted out.
Specifications subject to change without notice.
–2–
REV. A
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