AD7228ABP

更新时间： 2024-02-04 09:01:13

品牌	Logo	应用领域
亚德诺 - ADI		转换器数模转换器信息通信管理
页数	文件大小	规格书
8页	209K
描述
LC2MOS Octal 8-Bit DAC

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技术参数
数据手册

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AD7228ABP 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	DIP	包装说明：	CERDIP-24
针数：	24	Reach Compliance Code：	not_compliant
ECCN代码：	3A001.A.2.C	HTS代码：	8542.39.00.01
风险等级：	5.07	Is Samacsys：	N
最大模拟输出电压：	10 V	最小模拟输出电压：
转换器类型：	D/A CONVERTER	输入位码：	BINARY
输入格式：	PARALLEL, 8 BITS	JESD-30 代码：	R-GDIP-T24
JESD-609代码：	e0	最大线性误差 (EL)：	0.195%
标称负供电电压：	-5 V	位数：	8
功能数量：	1	端子数量：	24
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	CERAMIC, GLASS-SEALED	封装代码：	DIP
封装等效代码：	DIP24,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	12/15, GND/-5 V	认证状态：	Not Qualified
座面最大高度：	5.08 mm	最大稳定时间：	5 µs
子类别：	Other Converters	最大压摆率：	22 mA
表面贴装：	NO	技术：	MOS
温度等级：	MILITARY	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.62 mm	Base Number Matches：	1

AD7228ABP 数据手册

AD7228A

Table II. Unipolar Code Table

Mismatch between R1 and R2 causes gain and offset errors, and

therefore, these resistors must match and track over temperature.

D AC Latch Contents

Once again, the AD7228A can be operated from single supply

or from dual supplies. T able III shows the digital code versus

output voltage relationship for the circuit of Figure 8 with

R1 = R2.

MSB

LSB

Analog O utput

255

+V_REF

1 1 1 1

1 0 0 0

0 1 1 1

0 0 0 0

1 1 1 1

0 0 0 1

0 0 0 0

1 1 1 1

0 0 0 1

0 0 0 0

256

129

256

+V_REF

AC REFERENCE SIGNAL

V_REF

128

In some applications it may be desirable to have an ac signal ap-

plied as the reference input to the AD7228A. T he AD7228A

has multiplying capability within the upper (+10 V) and lower

(+2 V) limits of reference voltage when operated with dual sup-

plies. T herefore, ac signals need to be ac coupled and biased up

before being applied to the reference input. Figure 9 shows a

sine-wave signal applied to the reference input of the AD7228A.

For input frequencies up to 50 kHz, the output distortion typi-

cally remains less than 0.1%. T he typical 3 dB bandwidth for

small signal inputs is 800 kHz.

+V_REF

= +

256

127

256

0 V

Note: 1 LSB = (V_REF)(2^–8) = V_REF

256

BIP O LAR O UTP UT O P ERATIO N

Each of the DACs on the AD7228A can be individually config-

ured for bipolar output operation. T his is possible using one ex-

ternal amplifier and two resistors per channel. Figure 8 shows a

circuit used to implement offset binary coding (bipolar opera-

tion) with DAC1 of the AD7228A. In this case

V_OUT= 1 +

• D •V

–

• V

(

REF

(

)

REF

With R1 = R2

V_OUT= (2D₁– 1) • (V_REF

)

where D₁is a fractional representation of the digital word in

latch 1 of the AD7228A. (0 ≤ D₁≤ 255/256)

Figure 9. Applying a AC Signal to the AD7228A

TIMING D ESKEW

A common problem in AT E applications is the slowing or

“rounding-off” of signal edges by the time they reach the

pin-driver circuitry. T his problem can easily be overcome by

“squaring-up” the edge at the pin-driver. However, since each

edge will not have been “rounded-off” by the same extent, this

“squaring-up” could lead to incorrect timing relationship be-

tween signals. T his effect is shown in Figure 10a.

Figure 8. Bipolar Output Circuit

Table III. Bipolar Code Table

D AC Latch Contents

MSB

LSB

Analog O utput

Figure 10a. Tim e Skewing Due to Slowing of Edges

127

+V_REF

1 1 1 1

1 0 0 0

0 1 1 1

0 0 0 0

1 1 1 1

0 0 0 1

0 0 0 0

1 1 1 1

0 0 0 1

0 0 0 0

T he circuit of Figure 10b shows how two DACs of the

128

AD7228A can help in overcoming this problem. T he same two

signals are applied to this circuit as were applied in Figure 10b.

T he output of each DAC is applied to one input of a high-speed

comparator, and the signals are applied to the other inputs.

Varying the output voltage of the DAC effectively varies the

trigger point at which the comparator flips. T hus the timing re-

lationship between the two signals can be programmably cor-

rected (or deskewed) by varying the code to the DAC of the

AD7228A. In a typical application, the code is loaded to the

128

+V_REF

0 V

–V_REF

128

127

128

–V_REF

= –V_REF

–6–

REV. A

1...3 4 567 8

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