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AD7226TQ

更新时间： 2024-02-07 23:53:48
品牌 Logo 应用领域
亚德诺 - ADI 转换器数模转换器信息通信管理
页数 文件大小 规格书
12页 249K
描述
LC2MOS Quad 8-Bit D/A Converter

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AD7226TQ 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Not Recommended零件包装代码：DIP
包装说明：CERDIP-20针数：20
Reach Compliance Code：not_compliantECCN代码：3A001.A.2.C
HTS代码：8542.39.00.01风险等级：5.05
Is Samacsys：N最大模拟输出电压：5 V
最小模拟输出电压：-5 V转换器类型：D/A CONVERTER
输入位码：BINARY输入格式：PARALLEL, 8 BITS
JESD-30 代码：R-GDIP-T20JESD-609代码：e0
最大线性误差 (EL)：0.3906%标称负供电电压：-5 V
位数：8功能数量：4
端子数量：20最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装等效代码：DIP20,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT APPLICABLE电源：12/15, GND/-5 V
认证状态：Not Qualified座面最大高度：5.08 mm
最大稳定时间：20 µs标称安定时间 (tstl)：3 µs
子类别：Other Converters最大压摆率：13 mA
标称供电电压：15 V表面贴装：NO
技术：BICMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn63Pb37)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT APPLICABLE宽度：7.62 mm
Base Number Matches：1

AD7226TQ 数据手册

 浏览型号AD7226TQ的Datasheet PDF文件第4页浏览型号AD7226TQ的Datasheet PDF文件第5页浏览型号AD7226TQ的Datasheet PDF文件第6页浏览型号AD7226TQ的Datasheet PDF文件第8页浏览型号AD7226TQ的Datasheet PDF文件第9页浏览型号AD7226TQ的Datasheet PDF文件第10页 
AD7226  
Figure 10. Dynam ic Response (VSS = –5 V)  
Figure 9. Zero Code Error vs. Tem perature  
SP ECIFICATIO N RANGES  
In order for the DACs to operate to their specifications, the ref-  
erence voltage must be at least 4 V below the VDD power supply  
voltage. T his voltage differential is required for correct genera-  
tion of bias voltages for the DAC switches.  
T he AD7226 is specified to operate over a VDD range from  
+12 V ± 5% to +15 V ± 10% (i.e., from +11.4 V to +16.5 V)  
with a VSS of –5 V ± 10%. Operation is also specified for a  
single +15 V ± 5% VDD supply. Applying a VSS of –5 V results  
in improved zero code error, improved output sink capability  
with outputs near AGND and improved negative-going settling-  
time.  
Figure 11a. Positive-Step Settling-Tim e (VSS = –5 V)  
Performance is specified over a wide range of reference voltages  
from 2 V to (VDD – 4 V) with dual supplies. T his allows a range  
of standard reference generators to be used such as the AD580,  
a +2.5 V bandgap reference and the AD584, a precision +10 V  
reference. Note that in order to achieve an output voltage range  
of 0 V to +10 V a nominal +15 V ± 5% power supply voltage is  
required by the AD7226.  
SETTLING TIME  
T he output stage of the buffer amplifiers consists of a bipolar  
NPN transistor from the VDD line and a constant current load to  
VSS. VSS is the negative power supply for the output buffer am-  
plifiers. As mentioned in the op amp section, in single supply  
operation the NMOS transistor will come out of saturation as  
the output voltage approaches AGND and will act as a resistive  
load of approximately 2 kΩ to AGND. As a result, the settling-  
time for negative-going signals approaching AGND in single  
supply operation will be longer than for dual supply operation  
where the current load of 400 µA is maintained all the way down  
to AGND. Positive-going settling-time is not affected by VSS.  
Figure 11b. Negative-Step Settling-Tim e (VSS = –5 V)  
GRO UND MANAGEMENT  
AC or transient voltages between AGND and DGND can cause  
noise at the analog output. T his is especially true in micropro-  
cessor systems where digital noise is prevalent. T he simplest  
method of ensuring that voltages at AGND and DGND are  
equal is to tie AGND and DGND together at the AD7226. In  
more complex systems where the AGND and DGND intertie is  
on the backplane, it is recommended that two diodes be con-  
nected in inverse parallel between the AD7226 AGND and  
DGND pins (IN914 or equivalent).  
T he settling-time for the AD7226 is limited by the slew-rate of  
the output buffer amplifiers. T his can be seen from Figure 10  
which shows the dynamic response for the AD7226 for a full  
scale change. Figures 11a and 11b show expanded settling-time  
photographs with the output waveforms derived from a differen-  
tial input to an oscilloscope. Figure 11a shows the settling-time  
for a positive-going step and Figure 11b shows the settling-time  
for a negative-going output step.  
–7–  
REV. A  
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