Datasheet > AD694BRZ-REEL7

AD694BRZ-REEL7

更新时间： 2024-01-19 10:36:16

品牌	Logo	应用领域
亚德诺 - ADI		光电二极管
页数	文件大小	规格书
16页	166K
描述
IC IC,TRANSDUCER SIGNAL CONDITIONER,BIPOLAR,SOP,16PIN,PLASTIC, Analog IC:Other

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AD694BRZ-REEL7 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	包装说明：	SOP, SOP16,.4
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	7.99
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e3
湿度敏感等级：	1	端子数量：	16
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP16,.4	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	225
电源：	24 V	认证状态：	Not Qualified
子类别：	Other Analog ICs	标称供电电压 (Vsup)：	24 V
表面贴装：	YES	技术：	BIPOLAR
温度等级：	INDUSTRIAL	端子面层：	MATTE TIN
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	40
Base Number Matches：	1

AD694BRZ-REEL7 数据手册

AD694

Figure 4. Using Optional Pass Transistor to Minimize Self-Heating Errors; Dual Supply Operation Shown

POWER DISSIPATION CONSIDERATIONS

P(_TOT) = 2 mA × 24 V + (24 V – 10 V) × 1 mA + (24 V – 0 V) × 20 mA

The AD694 is rated for operation over its specified temperature

without the use of an external pass transistor. However, it is

possible to exceed the absolute maximum power dissipation,

with some combinations of power supply voltage and voltage

reference load. The internal dissipation of the part can be calcu-

lated to determine if there is a chance that the absolute maxi-

mum dissipation may be exceeded. The die temperature must

never exceed 150°C.

= 48 mW + 14 mW + 480 mW = 542 mW

Using θ_JCof 30°C/W and θ_CAof 70°C/W (from specifications

page), the junction temperature is:

T_J= 542 mW (30°C/W + 70°C/W) + 50°C = 104.2°C

The junction temperature is in the safe region.

Internal power dissipation can be reduced either by reducing the

value of θ_CAthrough the use of air flow or heat sinks, or by re-

ducing P_TOTof the AD694 through the use of an external pass

transistor. Figure 5 shows the maximum case and still air tem-

peratures for a given level of power dissipation.

Total power dissipation (P_TOT), is the sum of power dissipated

by the internal amplifiers, P (Standing), the voltage reference,

P(V_REF) and the current output stage, P(I_OUT) as follows:

P_TOT= P (Standing) + P (V_REF) + P (I_OUT

)

where:

P (Standing) = 2 mA (max) × V_S

P (V_REF) = (V_S– V_REF) × I_VREF

P(I_OUT) (V_S– V_OUT) × I_OUT(max):

_OUT(max) may be the max expected operating cur-

rent, or the overdriven current of the device.

P(I_OUT) drops to (2 V × I_OUT) if a pass transistor

is used.

Definitions:

_REF= output voltage of reference

_VREF= output current of reference

V_S= supply voltage

_OUT= voltage at I_OUTpin.

An appropriate safety factor should be added to P_TOT

Figure 5. Internal Power Dissipation in mW

The junction temperature may be calculated with the following

formula:

ADJUSTMENT PROCEDURES

The following sections describe methods for trimming the out-

put current offset, the span, and the voltage reference.

T_J= P_TOT(θ_JC+ θ_CA) + T_AMBIENT

_JCis the thermal resistance between the chip and the package

(case), θ_CAis the thermal resistance between the case and its

surroundings and is determined by the characteristics of the

thermal connection of the case to ambient.

ADJUSTING 4 mA ZERO

The 4 mA zero current may be adjusted over the range of 2 mA

to 4.8 mA to accommodate large input signal offsets, or to allow

small adjustment in the zero current. The zero may be adjusted

by pulling up or down on Pin 6 (4 mA Adj) to increase or de-

crease the nominal offset current. The 4 mA Adj. (Pin 6) should

not be driven to a voltage greater than 1 V. The arrangement of

For example, assume that the part is operating with a V_Sof 24 V

in the CERDIP package at 50°C, with a 1 mA load on the 10 V

reference. Assume that I_OUTis grounded and that the max I_OUT

would be 20 mA. The internal dissipation would be:

REV. B

–7–

1...4 5 678 9 10...16

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