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AD677JR-REEL PDF预览

AD677JR-REEL

更新时间: 2024-01-04 19:54:54
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 信息通信管理光电二极管转换器
页数 文件大小 规格书
17页 1110K
描述
1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO28, PLASTIC, SOIC-28

AD677JR-REEL 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP,针数:28
Reach Compliance Code:unknown风险等级:5.66
最大模拟输入电压:10 V最小模拟输入电压:-10 V
转换器类型:ADC, SUCCESSIVE APPROXIMATIONJESD-30 代码:R-PDSO-G28
JESD-609代码:e0长度:17.9 mm
湿度敏感等级:5标称负供电电压:-12 V
模拟输入通道数量:1位数:16
功能数量:1端子数量:28
最高工作温度:70 °C最低工作温度:
输出位码:BINARY输出格式:SERIAL
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):240采样速率:0.1 MHz
采样并保持/跟踪并保持:SAMPLE座面最大高度:2.65 mm
标称供电电压:12 V表面贴装:YES
技术:BICMOS温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.5 mm
Base Number Matches:1

AD677JR-REEL 数据手册

 浏览型号AD677JR-REEL的Datasheet PDF文件第4页浏览型号AD677JR-REEL的Datasheet PDF文件第5页浏览型号AD677JR-REEL的Datasheet PDF文件第6页浏览型号AD677JR-REEL的Datasheet PDF文件第8页浏览型号AD677JR-REEL的Datasheet PDF文件第9页浏览型号AD677JR-REEL的Datasheet PDF文件第10页 
AD677  
PIN DESCRIPTION  
Description  
DIP Pin SOIC Pin  
Type  
Name  
1
1
SAMPLE  
DI  
VIN Acquisition Control Pin. Active HIGH. During conversion, SAMPLE  
controls the suite of the internal sample-hold amplifier and the falling edge  
initiates conversion. During calibration, SAMPLE should be held LOW. If  
HIGH during calibration, diagnostic information will appear on SDATA.  
2
2
CLK  
DI  
Master Clock Input. The AD677 requires 17 clock pulses to execute a  
conversion. CLK is also used to derive SCLK.  
3
4
3
SDATA  
DGND  
VCC  
DO  
P
Serial Output Data Controlled by SCLK.  
Digital Ground.  
6, 7  
8
5
P
+12 V Analog Supply Voltage.  
Analog Ground.  
8
12  
15  
16  
17  
21  
22, 23  
26  
27  
AGND  
P
.9  
10  
11  
12  
13  
14  
15  
AGND SENSE AI  
Analog Ground Sense.  
VIN  
AI  
AI  
P
Analog Input Voltage.  
VREF  
VEE  
External Voltage Reference Input.  
–12 V Analog Supply Voltage.  
+5 V Logic Supply Voltage.  
Clock Output for Data Read, derived from CLK.  
VDD  
P
SCLK  
BUSY  
DO  
DO  
Status Line for Converter. Active HIGH, indicating a conversion or  
calibration in progress.  
16  
28  
CAL  
DI  
_
Calibration Control Pin.  
6, 7  
4, 5, 9, 10, 11, NC  
13, 14, 18, 19,  
20, 24, 25  
No Connection. No connections should be made to these pins.  
Type: AI = Analog Input  
DI = Digital Input  
DO = Digital Output  
P = Power  
28  
27  
26  
25  
24  
23  
22  
21  
20  
1
CAL  
SAMPLE  
CLK  
SAMPLE  
1
16  
15  
14  
13  
12  
11  
10  
CAL  
2
3
BUSY  
SCLK  
BUSY  
SCLK  
CLK  
2
3
SDATA  
NC  
SDATA  
4
5
NC  
NC  
V
DGND  
4
5
6
7
8
AD677  
TOP VIEW  
(Not to Scale)  
DD  
NC  
V
V
EE  
CC  
6
V
DGND1  
DD1  
V
NC  
NC  
REF  
V
7
DGND2  
DD2  
AD677  
TOP VIEW  
(Not to Scale)  
V
IN  
V
8
V
CC  
EE  
AGND  
9
AGND  
SENSE  
9
NC  
NC  
NC  
10  
11  
12  
13  
14  
19  
18  
NC  
NC  
NC = NO CONNECT  
NC  
AGND  
NC  
DIP Pinout  
V
17  
16  
REF  
V
IN  
15  
AGND  
NC  
SENSE  
NC = NO CONNECT  
SOIC Pinout  
–6–  
REV. A  

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