AD671
Upon receipt of an ENCODE command, the first 3-bit flash
converts the analog input voltage. The 3-bit result is passed to a
correction logic register and a segmented current output DAC.
The DAC output is connected through a resistor (within the
Range/Span Select Block) to AIN. A residue voltage is created
by subtracting the DAC output from AIN, which is less than
one eighth of the full-scale analog input. The second flash has
an input range that is configured with one bit of overlap with the
previous DAC. The overlap allows for errors during the flash
conversion. The first residue voltage is connected to the second
3-bit flash and to the noninverting input of a high speed, differ-
ential, gain-of-four amplifier. The second flash result is passed
to the correction logic register and to the second segmented cur-
rent output DAC. The output of the second DAC is connected
to the inverting input of the differential amplifier. The differen-
tial amplifier output is connected to a two step backend 8-bit
flash. This 8-bit flash consists of coarse and fine flash convert-
ers. The result of the coarse 4-bit flash converter, also config-
ured to overlap one bit of DAC 2, is connected to the correction
logic register and selects one of 16 resistors from which the fine
4-bit flash will establish its span voltage. The fine 4-bit flash is
connected directly to the output latches.
The closed-loop output impedance of an op amp is equal to the
open loop output impedance (usually a few hundred ohms) di-
vided by the loop gain at the frequency of interest. It is often
assumed that loop gain of a follower-connected op amp is suffi-
ciently high to reduce the closed-loop output impedance to a
negligibly small value, particularly if the input signal is low
frequency. At higher frequencies the open-loop gain is lower,
increasing the output impedance which decreases the instanta-
neous analog input voltage and produces an error.
The recommended wideband, fast settling input amplifiers for
use with the AD671 are the AD841, AD843, AD845 or the
AD847. The AD841 is unity gain stable and recommended as a
follower connected op amp. The AD843 and AD845 FET in-
puts make them ideal for high speed sample-and-hold amplifiers
and the AD847 can be used as a low power, high speed buffer.
Figure 4 shows the AD841 driving the AD671. As shown in the
figure the analog input voltage should be produced with respect
to the ACOM pin.
17
23
24
The AD671 will flag an out-of-range condition when the input
voltage exceeds the analog input range. OTR (Pin 14) is active
HIGH when an out of range high or low condition exists. Bits
1–12 are HIGH when the analog input voltage is greater than
the selected input range and LOW when the analog input is less
than the selected input range.
VLOGIC
VCC
VEE
11
4
5
1
10
20
AD841
6
BIT1
AIN
+
12
BIT12
±
5V
22
18
19
21
16
–
ACOM
DCOM
REF IN
ENCODE
15
14
13
DAV
OTR
MSB
+
5V REF
The AD671 uses a very high speed current output DAC to sub-
tract a known voltage from the analog input. This results in very
fast steps of current at the analog input. It is important to recog-
nize that the signal source driving the analog input of the
AD671 must be capable of maintaining the input voltage under
dynamically-changing load conditions. When the AD671 starts
its conversion cycle, the subtraction DAC will sink up to 5 mA
(see Figure 3) from the source driving the analog input. The
source must respond to this current step by settling the input
voltage back to a fraction of an LSB before the AD671 makes its
final 12-bit decision.
BPO/UPO
AD671
Figure 4. Input Buffer Amplifier
The AD671 uses a standard +5 volt reference. The initial accu-
racy and temperature stability of the reference can be selected to
meet specific system requirements. Like the analog input, fast
switching input-dependent currents are modulated at the refer-
ence input pin (REF IN–Pin 19). However, unlike the analog
input the reference input is held at a constant +5 volts with the
use of capacitor. The recommended reference is the AD586, a
+5 V precision reference with an output buffer amplifier. Fig-
ure 5 shows the AD671 configured in the ±5 V input range.
The 6.8 µF capacitor maintains a constant +5 volts under the
dynamically changing load conditions. An optional 1 µF noise
reduction capacitor can be connected to the AD586, further re-
ducing broadband output noise. To minimize ground voltage
drops the AD586’s ground pin should be tied as close as pos-
sible to the AD671’s ACOM pin. See Figures 20, 21 and 22 for
PCB layout recommendations.
IIN
+
–
R
A/D
DAC
IA/D
IDAC
AD671
Figure 3. Driving the Analog Input
Unlike successive approximation A/Ds, where the input voltage
must settle to a fraction of a 12-bit LSB before each successive
bit decision is made, the AD671 requires the analog input volt-
age settle to within 12 bits before the third flash conversion,
approximately 200 ns. This “free” 200 ns is useful in applica-
tions requiring a sample-and-hold amplifier (SHA), overlapping
the SHA’s hold mode settling time within the 200 ns window
will increase total system throughput. See the “Discrete Sample-
and-Hold” section for a high speed SHA application.
–8–
REV. B
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