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AD6642EBZ PDF预览

AD6642EBZ

更新时间: 2024-02-26 08:32:45
品牌 Logo 应用领域
亚德诺 - ADI 接收机
页数 文件大小 规格书
32页 1156K
描述
Dual IF Receiver

AD6642EBZ 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:BGA
包装说明:LFBGA, BGA144,12X12,32针数:144
Reach Compliance Code:compliantECCN代码:5A991.B
HTS代码:8542.39.00.01风险等级:5.14
JESD-30 代码:S-PBGA-B144JESD-609代码:e3
长度:10 mm湿度敏感等级:1
功能数量:1端子数量:144
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LFBGA
封装等效代码:BGA144,12X12,32封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):225
电源:1.8 V认证状态:Not Qualified
座面最大高度:1.4 mm子类别:Other Telecom ICs
最大压摆率:0.291 mA标称供电电压:1.8 V
表面贴装:YES技术:CMOS
电信集成电路类型:RF AND BASEBAND CIRCUIT温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10 mm
Base Number Matches:1

AD6642EBZ 数据手册

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AD6642  
SPECIFICATIONS  
DC SPECIFICATIONS  
AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless  
otherwise noted.  
Table 1.  
Parameter  
Temperature  
Min  
Typ  
Max  
Unit  
RESOLUTION  
Full  
11  
Bits  
ACCURACY  
No Missing Codes  
Offset Error  
Gain Error  
Differential Nonlinearity (DNL)1  
Integral Nonlinearity (INL)1  
MATCHING CHARACTERISTIC  
Offset Error  
Full  
Full  
Full  
Full  
Full  
Guaranteed  
2
3
0.1  
0.2  
−4.5  
−2.4  
7.4  
7
0.5  
0.5  
mV  
% FSR  
LSB  
LSB  
Full  
Full  
2.5  
1
8.3  
3
mV  
% FSR  
Gain Error  
TEMPERATURE DRIFT  
Offset Error  
Gain Error  
Full  
Full  
2
40  
ppm/°C  
ppm/°C  
ANALOG INPUT  
Input Range  
Full  
Full  
Full  
Full  
1.4  
1.75  
0.9  
20  
2.0  
V p-p  
V
kΩ  
pF  
Input Common-Mode Voltage  
Input Resistance (Differential)  
Input Capacitance2  
POWER SUPPLIES  
Supply Voltage  
AVDD  
5
Full  
Full  
1.7  
1.7  
1.8  
1.8  
1.9  
1.9  
V
V
DRVDD  
Supply Current  
1
IAVDD  
Full  
Full  
265  
79  
291  
89  
mA  
mA  
IDRVDD1 (1.8 V LVDS)  
POWER CONSUMPTION  
Sine Wave Input1  
Standby Power3  
Power-Down Power  
Full  
Full  
Full  
619  
83  
4.5  
684  
18  
mW  
mW  
mW  
1 Measured with a 10 MHz, 0 dBFS sine wave, with 100 Ω termination on each LVDS output pair.  
2 Input capacitance refers to the effective capacitance between one differential input pin and AGND.  
3 Standby power is measured with a dc input and the CLKx pins inactive (set to AVDD or AGND).  
Rev. 0 | Page 4 of 32  
 
 

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