Datasheet > AD6642EBZ

AD6642EBZ

更新时间： 2024-01-12 18:41:45

品牌	Logo	应用领域
亚德诺 - ADI		接收机
页数	文件大小	规格书
32页	1156K
描述
Dual IF Receiver

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AD6642EBZ 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	BGA
包装说明：	LFBGA, BGA144,12X12,32	针数：	144
Reach Compliance Code：	compliant	ECCN代码：	5A991.B
HTS代码：	8542.39.00.01	风险等级：	5.14
JESD-30 代码：	S-PBGA-B144	JESD-609代码：	e3
长度：	10 mm	湿度敏感等级：	1
功能数量：	1	端子数量：	144
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFBGA
封装等效代码：	BGA144,12X12,32	封装形状：	SQUARE
封装形式：	GRID ARRAY, LOW PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	225
电源：	1.8 V	认证状态：	Not Qualified
座面最大高度：	1.4 mm	子类别：	Other Telecom ICs
最大压摆率：	0.291 mA	标称供电电压：	1.8 V
表面贴装：	YES	技术：	CMOS
电信集成电路类型：	RF AND BASEBAND CIRCUIT	温度等级：	INDUSTRIAL
端子面层：	MATTE TIN	端子形式：	BALL
端子节距：	0.8 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	10 mm
Base Number Matches：	1

AD6642EBZ 数据手册

Dual IF Receiver

AD6642

FEATURES

FUNCTIONAL BLOCK DIAGRAM

AVDD

AGND

DRVDD DRGND

11-bit, 200 MSPS output data rate per channel

Integrated noise shaping requantizer (NSR)

Performance with NSR enabled

SNR: 75.5 dBFS in 40 MHz band to 70 MHz @ 185 MSPS

SNR: 73.7 dBFS in 60 MHz band to 70 MHz @ 185 MSPS

Performance with NSR disabled

SNR: 66.5 dBFS to 70 MHz @ 185 MSPS

SFDR: 83 dBc to 70 MHz @ 185 MSPS

Low power: 0.62 W @ 185 MSPS

AD6642

DC0±AB

D0±AB

VIN+A

VIN–A

VCMA

VIN+B

VIN–B

VCMB

PIPELINE

ADC

NOISE SHAPING

REQUANTIZER

NOISE SHAPING

REQUANTIZER

PIPELINE

ADC

D10±AB

MODE

SYNC

PDWN

REFERENCE

1.8 V analog supply operation

1.8 V LVDS (ANSI-644 levels) output

1-to-8 integer clock divider

CLOCK

DIVIDER

SERIAL PORT

Internal ADC voltage reference

SCLK SDIO

CSB

CLK+ CLK–

1.75 V p-p analog input range (programmable to 2.0 V p-p)

Differential analog inputs with 800 MHz bandwidth

95 dB channel isolation/crosstalk

Figure 1.

PRODUCT HIGHLIGHTS

Serial port control

User-configurable built-in self-test (BIST) capability

Energy-saving power-down modes

1. Two ADCs are contained in a small, space-saving,

10 mm × 10 mm × 1.4 mm, 144-ball CSP_BGA package.

2. Pin selectable noise shaping requantizer (NSR) function

that allows for improved SNR within a reduced bandwidth

of up to 60 MHz at 185 MSPS.

3. LVDS digital output interface configured for low cost

FPGA families.

4. 120 mW per ADC core power consumption.

5. Operation from a single 1.8 V supply.

6. Standard serial port interface (SPI) that supports various

product features and functions, such as data formatting

(offset binary or twos complement), NSR, power-down,

test modes, and voltage reference mode.

APPLICATIONS

Communications

Diversity radio and smart antenna (MIMO) systems

Multimode digital receivers (3G)

WCDMA, LTE, CDMA2000

WiMAX, TD-SCDMA

I/Q demodulation systems

General-purpose software radios

7. On-chip integer 1-to-8 input clock divider and multichip

sync function to support a wide range of clocking schemes

and multichannel subsystems.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

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