Datasheet > AD6636BBCZ1

AD6636BBCZ1

更新时间： 2022-11-24 21:58:05

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
72页	1741K
描述
150 MSPS Wideband Digital Down-Converter (DDC)

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AD6636BBCZ1 数据手册

AD6636

GENERAL TIMING CHARACTERISTICS

Table 3. General Timing Characteristics^{1, 2}

Parameter

Temp

Test Level

Min

Typ

Max

Unit

CLK TIMING REQUIREMENTS

t_CLK

t_CLKL

t_CLKH

t_CLKSKEW

CLKx Period (x = A, B, C, D)

Full

6.66

1.71

1.70

t_CLK− 1.3

CLKx Width Low (x = A, B, C, D)

CLKx Width High (x = A, B, C, D)

CLKA to CLKx Skew (x = B, C, D)

0.5 × t_CLK

INPUT WIDEBAND DATA TIMING REQUIREMENTS

t_SI

0.75

1.13

3.37

1.11

5.98

INx [15:0] to ↑CLKx Setup Time (x = A, B, C, D)

INx [15:0] to ↑CLKx Hold Time (x = A, B, C, D)

EXPx [2:0] to ↑CLKx Setup Time (x = A, B, C, D)

EXPx [2:0] to ↑CLKx Hold Time (x = A, B, C, D)

↑CLKx to EXPx[2:0] Delay (x = A, B, C, D)

t_HI

t_SEXP

t_HEXP

t_DEXP

10.74

PARALLEL OUTPUT PORT TIMING REQUIREMENTS (MASTER)

t_DPREQ

t_DPP

Full

1.77

2.07

0.48

0.38

0.23

4.59

0.90

3.86

5.29

5.49

5.35

4.95

↑PCLK to ↑Px REQ Delay (x = A, B, C)

↑PCLK to Px [15:0] Delay (x = A, B, C)

↑PCLK to Px IQ Delay (x = A, B, C)

t_DPIQ

t_DPCH

t_DPGAIN

t_SPA

↑PCLK to Px CH[2:0] Delay (x = A, B, C)

↑PCLK to Px Gain Delay (x = A, B, C)

Px ACK to ↑PCLK Setup Time (x = A, B, C)

Px ACK to ↑PCLK Hold Time (x = A, B, C)

t_HPA

PARALLEL OUTPUT PORT TIMING REQUIREMENTS (SLAVE)

t_PCLK

t_PCLKL

t_PCLKH

t_DPREQ

t_DPP

PCLK Period

PCLK Low Period

PCLK High Period

Full

5.0

1.7

0.7

4.72

4.8

0.5 × t_PCLK

8.87

↑PCLK to ↑Px REQ Delay (x = A, B, C)

↑PCLK to Px [15:0] Delay (x = A, B, C)

↑PCLK to Px IQ Delay (x = A, B, C)

↑PCLK to Px CH[2:0] Delay (x = A, B, C)

↑PCLK to Px Gain Delay (x = A, B, C)

Px ACK to ↓PCLK Setup Time (x = A, B, C)

Px ACK to ↓PCLK Hold Time (x = A, B, C)

8.48

t_DPIQ

t_DPCH

t_DPGAIN

t_SPA

4.83

4.88

5.08

6.09

1.0

10.94

10.09

11.49

t_HPA

MISC PINS TIMING REQUIREMENTS

t_RESET

t_DIRP

t_SS

RESET Width Low

Full

CPUCLK/SCLK to IRP Delay

SYNC(0, 1, 2, 3) to ↑CLKA Setup Time

SYNC(0, 1, 2, 3) to ↑CLKA Hold Time

7.5

0.87

0.67

t_HS

¹All timing specifications are valid over the VDDCORE range of 1.7 V to 1.9 V and the VDDIO range of 3.0 V to 3.6 V.

²C_LOAD= 40 pF on all outputs, unless otherwise noted.

Rev. 0 | Page 6 of 72

1...3 4 567 8 9...72

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