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AD6630AR-REEL PDF预览

AD6630AR-REEL

更新时间: 2024-02-12 08:18:34
品牌 Logo 应用领域
亚德诺 - ADI 消费电路商用集成电路光电二极管
页数 文件大小 规格书
8页 132K
描述
Differential, Low Noise IF Gain Block with Output Clamping

AD6630AR-REEL 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:0.300 INCH, PLASTIC, SOIC-16针数:16
Reach Compliance Code:unknown风险等级:5.81
商用集成电路类型:CONSUMER CIRCUITJESD-30 代码:R-PDSO-G16
JESD-609代码:e3长度:10.25 mm
湿度敏感等级:1功能数量:1
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
认证状态:COMMERCIAL座面最大高度:2.65 mm
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.25 V
表面贴装:YES技术:BIPOLAR
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:7.5 mm

AD6630AR-REEL 数据手册

 浏览型号AD6630AR-REEL的Datasheet PDF文件第2页浏览型号AD6630AR-REEL的Datasheet PDF文件第3页浏览型号AD6630AR-REEL的Datasheet PDF文件第4页浏览型号AD6630AR-REEL的Datasheet PDF文件第6页浏览型号AD6630AR-REEL的Datasheet PDF文件第7页浏览型号AD6630AR-REEL的Datasheet PDF文件第8页 
AD6630  
–1dB 15dB –9dB –2dB 15dB –5dB 24dB –5dB  
MAIN  
9dBm  
4dBm  
–15dBm  
–28dBm –29dBm –14dBm –23dBm–25dBm10dBm  
LOCAL  
OSCILLATOR  
AD6600  
AD6620  
DSP  
AD6630  
SAW  
SAW  
DIVERSITY  
ANTENNA  
–104dBm  
–43dBm  
–28dBm  
–16dBm  
–15dBm  
AD6630 INPUT  
–91dBm  
–30dBm  
–15dBm  
–3dBm  
AD6630 OUTPUT  
–67dBm  
–6dBm  
AD6600 INPUT  
–71dBm  
–10dBm  
+4dBm  
+9dBm  
+9dBm  
+9dBm  
+4dBm  
+4dBm  
–2dBm  
Figure 6. GSM Design Example  
This equation is derived from measured data at 170 MHz. Clamp  
levels vary with frequency, see Figure 5. Output clamp levels  
less than 8.5 dBm will result in damage to the clamp circuitry  
unless the absolute maximum input power is derated. Similarly,  
the output clamp level cannot be set higher than 12 dBm.  
THEORY OF OPERATION  
The AD6630 amplifier consists of two stages of gain. The first  
stage is differential. This differential amplifier provides good  
common-mode rejection to common-mode signals passed by  
the SAW filter. The second stage consists of matched current  
feedback amplifiers on each side of the differential pair. These  
amplifiers provide additional gain as well as output drive capa-  
bility. Gain set resistors for these stages are internal to the de-  
vice and cannot be changed, allowing fixed compensation for  
optimum performance.  
R
CLAMP  
GENERATOR  
V
EE  
Figure 7. Clamp Level Resistor  
Matching SAW Filters  
The AD6630 is designed to easily match to SAW filters. SAW  
filters are largely capacitive in nature. Normally a conjugate  
match to the load is desired for maximum power transfer.  
Clamping levels for the device are normally set by tying CLLO  
or CLHI pins to the negative supply. This internally sets bias  
points that generate symmetric clamping levels. Clamping is  
achieved primarily in the output amplifiers. Additional input  
stage clamping is provided for additional protection. Clamping  
levels may be adjusted to lower levels as discussed below.  
Another way to treat the problem is to make the SAW filter look  
purely resistive. If the SAW filter load looks resistive there is no  
lead or lag in the current vs. voltage. This may not preserve  
maximum power transfer, but maximum voltage swing will  
exist. All that is required to make the SAW filter input or output  
look real is a single inductor shunted across the input. When the  
correct value is used, the impedance of the SAW filter becomes  
real.  
APPLICATIONS  
The AD6630 provides several useful features to meet the needs  
of radio designers. The gain and low noise figure of the device  
make it perfect for providing interstage gain between differential  
SAW filters and/or analog-to-digital converters (ADC). Addi-  
tionally, the on-board clamping circuitry provides protection for  
sensitive SAW filters or ADCs. The fast recovery of the clamp  
circuit permits demodulation of constant envelope modulated  
IF signals by preserving the phase response during clamping.  
9.7⍀  
The following topics provide recommendations for using the  
AD6630 in narrowband, single carrier applications.  
400⍀  
47nH  
3pF  
15.2pF  
Adjusting Output Clamp Levels  
Normally, the output clamp level is set by tying either CLLO or  
CLHI to ground or VEE. It is possible to set the limit between  
8.5 dBm and 12 dBm levels by selecting the appropriate exter-  
nal resistor.  
Figure 8. Saw Filter Model (170 MHz)  
EVALUATION BOARD  
To set to a different level, CLLO and CLHI should be tied  
together and then through a resistor to ground. The value of the  
resistor can be selected using the following equation.  
Figures 9, 10 and 12 refer to the schematic and layout of the  
AD6630AR as used on Analog Devices’ GSM Diversity Re-  
ceiver Reference Design (only the IF section is shown). Figure  
14 references the schematic of the stand-alone AD6630 evalua-  
tion board and uses a similar layout. The evaluation board uses  
center tapped transformers to convert the input to a differential  
signal and AD6630 outputs to a single connector to simplify  
evaluation. C8, C9 and L2 are optional reactive components to  
tune the load for a particular IF frequency if desired.  
14.4OUTPUT  
R =  
CLAMP (dBm)  
0.0014  
REV. 0  
–5–  

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