150 MSPS Wideband
Digital Down-Converter (DDC)
AD6636
6 programmable digital AGC loops with 96 dB range
Synchronous serial I/O operation (SPI®-, SPORT-compatible)
Supports 8-bit or 16-bit microport modes
3.3 V I/O, 1.8 V CMOS core
User-configurable built-in self-test (BIST) capability
JTAG boundary scan
FEATURES
4/6 independent wideband processing channels
Processes 6 wideband carriers (UMTS, CDMA2000)
4 single-ended or 2 LVDS parallel input ports
(16 linear bit plus 3-bit exponent) running at 150 MHz
Supports 300 MSPS input using external interface logic
3 16-bit parallel output ports operating up to 200 MHz
Real or complex input ports
Quadrature correction and dc correction for complex inputs
Supports output rate up to 34 MSPS per channel
RMS/peak power monitoring of input ports
APPLICATIONS
Multicarrier, multimode digital receivers
GSM, EDGE, PHS, UMTS, WCDMA, CDMA2000, TD-SCDMA
Micro and pico cell systems, software radios
Broadband data applications
Programmable attenuator control for external gain ranging
3 programmable coefficient FIR filters per channel
2 decimating half-band filters per channel
Instrumentation and test equipment
Wireless local loop
In-building wireless telephony
FUNCTIONAL BLOCK DIAGRAM
FIR1
HB1
M = Byp, 2
FIR2
HB2
M = Byp, 2
MRCF
DRCF
M = 1-16
CIC5
M = 1-32
CRCF
M = 1-16
LHB
L = Byp, 2
CLKA
ADC A/AI
EXPA [2:0]
CLKB
NCO
NCO
NCO
NCO
NCO
NCO
FIR1
HB1
M = Byp, 2
FIR2
HB2
M = Byp, 2
MRCF
DRCF
M = 1-16
CIC5
M = 1-32
CRCF
M = 1-16
LHB
L = Byp, 2
PA
PB
PC
ADC B/AQ
EXPB [2:0]
CLKC
FIR1
HB1
M = Byp, 2
FIR2
HB2
M = Byp, 2
MRCF
DRCF
M = 1-16
CIC5
M = 1-32
CRCF
M = 1-16
LHB
L = Byp, 2
CMOS
REAL
PORTS
A, B,
AGC
ADC C/CI
EXPC [2:0]
CLKD
C,D
FIR1
HB1
M = Byp, 2
FIR2
HB2
M = Byp, 2
MRCF
DRCF
M = 1-16
CIC5
M = 1-32
CRCF
M = 1-16
LHB
L = Byp, 2
CMOS
COMPLEX
PORTS
(AI, AQ)
(BI, BQ)
FIR1
HB1
M = Byp, 2
FIR2
HB2
M = Byp, 2
MRCF
DRCF
M = 1-16
CIC5
M = 1-32
CRCF
M = 1-16
LHB
L = Byp, 2
LVDS
PORTS
AB, CD
ADC D/CQ
EXPD [2:0]
______
PEAK/
RMS
MEAS.
FIR1
HB1
M = Byp, 2
FIR2
HB2
M = Byp, 2
MRCF
DRCF
M = 1-16
RESET
CIC5
M = 1-32
CRCF
M = 1-16
LHB
L = Byp, 2
I,Q
CORR.
SYNC [3:0]
PLL CLOCK
MULTIPLIER
16-BIT
MICROPORT INTERFACE
SPORT/SPI INTERFACE
JTAG
NOTE: CHANNELS RENDERED AS
ARE AVAILABLE ONLY IN 6-CHANNEL PART
M = DECIMATION
L = INTERPOLATION
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
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