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AD6458ARS PDF预览

AD6458ARS

更新时间: 2024-02-05 18:44:37
品牌 Logo 应用领域
亚德诺 - ADI GSM
页数 文件大小 规格书
12页 270K
描述
GSM 3 V Receiver IF Subsystem

AD6458ARS 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP-20
针数:20Reach Compliance Code:unknown
ECCN代码:5A991.BHTS代码:8542.39.00.01
风险等级:5.87JESD-30 代码:R-PDSO-G20
JESD-609代码:e0功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SSOP20,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:3/3.3 V
认证状态:Not Qualified子类别:Other Telecom ICs
最大压摆率:0.022 mA标称供电电压:3.3 V
表面贴装:YES技术:BIPOLAR
电信集成电路类型:TELECOM CIRCUIT温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED

AD6458ARS 数据手册

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AD6458  
I/Q Convention  
The VFQO operates from 5 MHz to 50 MHz and is controlled  
by the voltage between VPOS and FLTR. In normal operation, a  
series RC network, forming the PLL loop filter, is connected  
from FLTR to VPOS. The use of an integral sample-hold system  
ensures that the frequency-control voltage on pin FLTR re-  
mains held during power-down, so reacquisition of the carrier  
occurs in less than 80 µs.  
The AD6458 is a complete IF receive subsystem. Although not  
a requirement for using the AD6458, most applications will use  
a high-side LO injection on pin LOIP (Pin 4) of the mixer. The  
I and Q convention is such that when a spectrum with I leading  
Q is presented to the input of the mixer, and a high-side LO is  
presented on pin LOIP, I still leads Q at the baseband output of  
the AD6458.  
In practice, the probability of a phase mismatch at power-up is  
high, so the worst-case linear settling period to full lock needs to  
be considered in making filter choices. This is typically < 80 µs  
for a quadrature phase error of ±3° at an IF of 13 MHz. Note  
that the VFQO always provides quadrature between its own I  
and Q outputs, but the phasing between it and the reference  
carrier will swing around the final value during the PLL’s set-  
tling time.  
Phase-Locked Loop  
The demodulators are driven by quadrature signals provided by  
a variable frequency quadrature oscillator (VFQO), phase-  
locked to a reference signal applied to Pin FREF. When this  
signal is at the IF, in-phase and quadrature baseband outputs  
are generated at the I output (IRXP and IRXN) and Q output  
(QRXP and QRXN), respectively. The quadrature accuracy of  
this VFQO is typically 2° at 13 MHz. A simplified diagram of  
the FREF input is shown in Figure 35.  
Bias System  
The AD6458 operates from a single supply, VPOS, usually 3.3 V,  
at a typical supply current of 9 mA at midgain and TA = +25°C.  
Any voltage from 3.0 V to 3.6 V may be used.  
V
POS  
5kΩ  
The bias system includes a fast acting active high CMOS-  
compatible power-up switch, allowing the part to idle at 1 µA  
when disabled. Biasing is generally proportional-to-absolute-  
temperature (PTAT) to ensure stable gain with temperature.  
Other special biasing techniques are used to ensure very accu-  
rate gain, stable over the full temperature range.  
20kΩ  
FREF  
5kΩ  
50µA PTAT  
Figure 35. Simplified Schematic of the FREF Interface  
OUTLINE DIMENSIONS  
Dimensions shown in inches and (mm).  
20-Lead Plastic SSOP  
(RS-20)  
0.295 (7.50)  
0.271 (6.90)  
20  
11  
1
10  
0.07 (1.78)  
0.078 (1.98)  
PIN 1  
0.066 (1.67)  
0.068 (1.73)  
0.037 (0.94)  
8°  
0°  
0.0256  
(0.65)  
BSC  
0.022 (0.559)  
0.008 (0.203)  
0.002 (0.050)  
SEATING  
PLANE  
0.009 (0.229)  
0.005 (0.127)  
–12–  
REV. 0  

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