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AD626B

更新时间： 2024-01-14 01:54:24
品牌 Logo 应用领域
亚德诺 - ADI 放大器
页数 文件大小 规格书
12页 169K
描述
Low Cost, Single Supply Differential Amplifier

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中文翻译

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AD626B 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：DIP
包装说明：DIP,针数：8
Reach Compliance Code：unknown风险等级：5.4
放大器类型：INSTRUMENTATION AMPLIFIER标称带宽 (3dB)：0.1 MHz
最小共模抑制比：55 dB最大输入失调电压：2500 µV
JESD-30 代码：R-PDIP-T8JESD-609代码：e3
长度：9.88 mm湿度敏感等级：NOT APPLICABLE
负供电电压上限：-18 V标称负供电电压 (Vsup)：-5 V
最大非线性：0.015%功能数量：1
端子数量：8最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT APPLICABLE
认证状态：COMMERCIAL座面最大高度：5.33 mm
标称压摆率：0.22 V/us子类别：Instrumentation Amplifier
供电电压上限：18 V标称供电电压 (Vsup)：5 V
表面贴装：NO温度等级：INDUSTRIAL
端子面层：MATTE TIN端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT APPLICABLE最大电压增益：100
最小电压增益：10标称电压增益：100
宽度：7.62 mmBase Number Matches：1

AD626B 数据手册

 浏览型号AD626B的Datasheet PDF文件第6页浏览型号AD626B的Datasheet PDF文件第7页浏览型号AD626B的Datasheet PDF文件第8页浏览型号AD626B的Datasheet PDF文件第9页浏览型号AD626B的Datasheet PDF文件第11页浏览型号AD626B的Datasheet PDF文件第12页 
AD626  
+INPUT  
–INPUT  
The output of A1 is connected to the input of A2 via a 100 kΩ  
(R12) resistor to facilitate the low-pass filtering of the signal of  
interest (see Low-Pass Filtering section).  
200k⍀  
200k⍀  
+IN  
–IN  
1
2
3
8
7
6
5
The 200 kΩ input impedance of the AD626 requires that the  
source resistance driving this amplifier be low in value (<1 kΩ)—  
this is necessary to minimize gain error. Also, any mismatch  
between the total source resistance at each input will affect gain  
accuracy and common-mode rejection (CMR). For example:  
when operating at a gain of 10, an 80 Ω mismatch in the source  
resistance between the inputs will degrade CMR to 68 dB.  
1/6  
ANALOG  
GND  
NOT  
CONNECTED  
G = 100  
G=30  
–V  
+V  
S
–V  
S
+V  
S
S
0.1␮F  
100k⍀  
FILTER  
0.1␮F  
OUT  
=
OUTPUT  
G
2
4
The output buffer, A2, operates at a gain of 2 or 20, thus setting  
the overall, precalibrated gain of the AD626 (with no external  
components) at 10 or 100. The gain is set by the feedback net-  
work around amplifier A2.  
AD626  
Figure 29. AD626 Configured for a Gain of 10  
+INPUT  
The output of amplifier A2 relies on a 10 kΩ resistor to –VS for  
“pulldown.” For single supply operation, (–VS = “GND”), A2  
can drive a 10 kΩ ground referenced load to at least +4.7 V.  
The minimum, nominally “zero,” output voltage will be 30 mV.  
For dual supply operation (±5 V), the positive output voltage  
swing will be the same as for a single supply. The negative swing  
will be to –2.5 V, at G = 100, limited by the ratio:  
200k⍀  
200k⍀  
+IN  
–IN  
–INPUT  
1
2
3
8
7
6
5
1/6  
ANALOG  
GND  
G = 100  
G=30  
–V  
+V  
–V  
S
+V  
S
S
R15 + R14  
–VS ×  
S
0.1␮F  
100k⍀  
FILTER  
0.1␮F  
OUTPUT  
R13 + R14 + R15  
OUT  
=
G
2
4
The negative range can be extended to –3.3 V (G = 100) and  
–4 V (G = 10) by adding an external 10 kΩ pulldown from the  
output to –VS. This will add 0.5 mA to the AD626’s quiescent  
current, bringing the total to 2 mA.  
AD626  
Figure 30. AD626 Configured for a Gain of 100  
The AD626’s 100 kHz bandwidth at G = 10 and 100 (a 10 MHz  
gain bandwidth) is much higher than can be obtained with low  
power op amps in discrete differential amplifier circuits. Fur-  
thermore, the AD626 is stable driving capacitive loads up to  
50 pF (G10) or 200 pF (G100). Capacitive load drive can be  
increased to 200 pF (G10) by connecting a 100 Ω resistor in  
series with the AD626’s output and the load.  
+INPUT  
200k⍀  
200k⍀  
+IN  
–IN  
–INPUT  
8
7
6
5
1
2
3
1/6  
R
H
ANALOG  
GND  
G = 100  
R
G
G=30  
–V  
+V  
–V  
S
+V  
S
S
S
ADJUSTING THE GAIN OF THE AD626  
100k⍀  
FILTER  
0.1␮F  
0.1␮F  
The AD626 is easily configured for gains of 10 or 100. Figure  
29 shows that for a gain of 10, Pin 7 is simply left unconnected;  
similarly, for a gain of 100, Pin 7 is grounded, as shown in Fig-  
ure 30.  
OUT  
=
G
OUTPUT  
2
4
CF  
FILTER  
(OPTIONAL)  
AD626  
1
CORNER FREQUENCY OF FILTER =  
Gains between 10 and 100 are easily set by connecting a vari-  
able resistance between Pin 7 and Analog GND, as shown in  
Figure 31. Because the on-chip resistors have an absolute toler-  
ance of ±20% (although they are ratio matched to within 0.1%),  
at least a 20% adjustment range must be provided. The values  
shown in the table in Figure 31 provide a good trade-off be-  
tween gain set range and resolution, for gains from 11 to 90.  
2␲CF (100k⍀)  
RESISTOR VALUES FOR GAIN ADJUSTMENT  
GAIN RANGE  
R
(⍀)  
R (⍀)  
H
G
4.99k  
802  
80  
11 – 20  
20 – 40  
40 – 80  
80 – 100  
100k  
10k  
1k  
2
100  
Figure 31. Recommended Circuit for Gain Adjustment  
–10–  
REV. C  
1...789101112

中文翻译

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