AD5933

更新时间： 2024-02-21 04:43:21

品牌	Logo	应用领域
亚德诺 - ADI		转换器
页数	文件大小	规格书
20页	689K
描述
1 MSPS 12-Bit Impedance Converter, Network Analyzer

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中文翻译

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技术参数
数据手册

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AD5933 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SSOP
包装说明：	SSOP,	针数：	16
Reach Compliance Code：	unknown	风险等级：	5.57
模拟集成电路 - 其他类型：	ANALOG CIRCUIT	JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e3	长度：	6.2 mm
湿度敏感等级：	1	功能数量：	1
端子数量：	16	最高工作温度：	125 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH	峰值回流温度（摄氏度）：	260
座面最大高度：	2 mm	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	2.7 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	温度等级：	AUTOMOTIVE
端子面层：	MATTE TIN	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	40	宽度：	5.3 mm
Base Number Matches：	1

AD5933 数据手册

AD5933

Preliminary Technical Data

Figure 11.

SDA line during the low period before the 9th clock pulse, but

the slave device will not pull it low. This is known as No

Acknowledge. The master will then take the data line low

during the low period before the 10th clock pulse, then high

during the 10th clock pulse to assert a STOP condition.

1. The master initiates data transfer by establishing a START

condition, defined as a high to low transition on the serial data

line SDA while the serial clock line SCL remains high. This

indicates that a data stream will follow. The slave responds to

the START condition and shift in the next 8 bits, consisting of a

7-bit slave address (MSB first) plus an R/W bit, which

determines the direction of the data transfer, i.e. whether data

will be written to or read from the slave device (0 = write, 1 =

read).

WRITING/READING TO THE AD5933

The interface specification defines several different protocols

for different types of read and write operations. The ones used

in the AD5933 are discussed below. The following abbreviations

are used:

The slave responds by pulling the data line low during the low

period before the ninth clock pulse, known as the acknowledge

bit, and holding it low during the high period of this clock

pulse. All other devices on the bus now remain idle while the

selected device waits for data to be read from or written to it. If

the R/W bit is a 0, then the master will write to the slave device.

If the R/W bit is a 1, the master will read from the slave device.

Start

Stop

Read

Write

Acknowledge

No Acknowledge

2. Data is sent over the serial bus in sequences of nine clock

pulses, 8 bits of data followed by an acknowledge bit, which can

be from the master or slave device. Data transitions on the data

line must occur during the low period of the clock signal and

remain stable during the high period, as a low to high transition

when the clock is high may be interpreted as a STOP signal. If

the operation is a write operation, the first data byte after the

slave address is a command byte. This tells the slave device what

to expect next. It may be an instruction telling the slave device

to expect a block write, or it may simply be a register address

that tells the slave where subsequent data is to be written. Since

data can flow in only one direction as defined by the R/W bit, it

is not possible to send a command to a slave device during a

read operation. Before doing a read operation, it may first be

necessary to do a write operation to tell the slave what sort of

read operation to expect and/or the address from which data is

to be read.

Write Byte/Command Byte

In this operation the master device sends a byte of data to the

slave device. The write byte can either be a data byte write to a

RAM location or can be a command operation.

To write data to a register the command sequence is as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the write

bit (low).

3. The addressed slave device asserts ACK on SDA.

4. The master sends a register address.

5. The slave asserts ACK on SDA.

6. The master sends a data byte.

3. When all data bytes have been read or written, stop

7. The slave asserts ACK on SDA.

conditions are established. In WRITE mode, the master will pull

the data line high during the 10th clock pulse to assert a STOP

condition. In READ mode, the master device will release the

8. The master asserts a STOP condition on SDA to end the

transaction.

Rev. PrA | Page 16 of 20

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中文翻译

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与AD5933相关器件

型号	品牌	获取价格	描述	数据表
AD5933BRSZ-U1	ADI	获取价格	IC SPECIALTY ANALOG CIRCUIT, PDSO16, LEAD FREE, MO-150AC, SSOP-16, Analog IC:Other
AD5933WYRSZ-REEL7	ADI	获取价格	1 MSPS, 12-Bit Impedance Converter, Network Analyzer
AD5933YRSZ	ADI	获取价格	1 MSPS, 12-Bit Impedance Converter, Network Analyzer
AD5933YRSZ-REEL7	ADI	获取价格	1 MSPS, 12-Bit Impedance Converter, Network Analyzer
AD5934	ADI	获取价格	250 kSPS, 12-Bit Impedance Converter, Network Analyzer
AD5934BRSZ-U1	ADI	获取价格	IC SPECIALTY ANALOG CIRCUIT, PDSO16, LEAD FREE, MO-150AC, SSOP-16, Analog IC:Other
AD5934YRSZ	ADI	获取价格	250 kSPS, 12-Bit Impedance Converter, Network Analyzer
AD5934YRSZ-REEL7	ADI	获取价格	250 kSPS, 12-Bit Impedance Converter, Network Analyzer
AD594	ADI	获取价格	Monolithic Thermocouple Amplifiers with Cold Junction Compensation
AD594/AD595	ADI	获取价格	Monolithic Thermocouple Amplifiers with Cold Junction Compensation

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