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AD5752

更新时间： 2024-02-02 12:31:36
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
32页 990K
描述
Complete, Dual, 12-/14-/16-Bit, Serial Input, Unipolar/Bipolar, Voltage Output DACs

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AD5752 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：HTSSOP, TSSOP24,.25针数：24
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.78
最大模拟输出电压：12 V最小模拟输出电压：-12 V
转换器类型：D/A CONVERTER输入位码：BINARY, OFFSET BINARY, 2'S COMPLEMENT BINARY
输入格式：SERIALJESD-30 代码：R-PDSO-G24
JESD-609代码：e3长度：7.8 mm
最大线性误差 (EL)：0.0244%标称负供电电压：-5 V
位数：16功能数量：1
端子数量：24最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：HTSSOP封装等效代码：TSSOP24,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, HEAT SINK/SLUG, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：3/5,+-5/+-15 V
认证状态：Not Qualified座面最大高度：1.2 mm
最大稳定时间：10 µs标称安定时间 (tstl)：10 µs
子类别：Other Converters标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：4.4 mmBase Number Matches：1

AD5752 数据手册

 浏览型号AD5752的Datasheet PDF文件第23页浏览型号AD5752的Datasheet PDF文件第24页浏览型号AD5752的Datasheet PDF文件第25页浏览型号AD5752的Datasheet PDF文件第27页浏览型号AD5752的Datasheet PDF文件第28页浏览型号AD5752的Datasheet PDF文件第29页 
AD5722/AD5732/AD5752  
CONTROL REGISTER  
The control register is addressed by setting the three REG bits to 011. The value written to the address and data bits determines the  
control function selected. The control register options are shown in Table 23 and Table 24.  
Table 23. Programming the Control Register  
MSB  
LSB  
R/  
0
Zero  
REG2 REG1 REG0 A2 A1 A0 DB15 to DB4  
DB3  
DB2  
DB1  
DB0  
W
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
0
0
0
1
0
1
N O P, data = don’t care  
0
Don’t care  
TSD enable  
Clamp enable  
CLR select SDO disable  
0
Clear, data = don’t care  
Load, data = don’t care  
0
Table 24. Explanation of Control Register Options  
Option  
Description  
NOP  
No operation instruction used in readback operations.  
Clear  
Load  
SDO Disable  
CLR Select  
Addressing this function sets the DAC registers to the clear code and updates the outputs.  
Addressing this function updates the DAC registers and, consequently, the DAC outputs.  
Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default).  
See Table 25 for a description of the CLR select operation.  
Clamp Enable Set by the user to enable the current-limit clamp. The channel does not power down upon detection of an overcurrent; the  
current is clamped at 20 mA (default).  
Cleared by the user to disable the current-limit clamp. The channel powers down upon detection of an overcurrent.  
TSD Enable  
Set by the user to enable the thermal shutdown feature. Cleared by the user to disable the thermal shutdown feature (default).  
Table 25. CLR Select Options  
Output CLR Value  
Bipolar Output Range  
CLR Select Setting  
Unipolar Output Range  
0
1
0 V  
Midscale  
0 V  
Negative full-scale  
POWER CONTROL REGISTER  
The power control register is addressed by setting the three REG bits to 010. This register allows the user to control and determine the  
power and thermal status of the AD5722/AD5732/AD5752. The power control register options are shown in Table 26 and Table 27.  
Table 26. Programming the Power Control Register  
MSB  
LSB  
DB15 to  
W
R/  
Zero REG2 REG1 REG0 A2 A1 A0 DB11  
DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
0
0
0
1
0
0
0
0
X
0
OCB  
X
OCA  
X
TSD  
X
X
PUB  
X
PUA  
Table 27. Power Control Register Functions  
Option Description  
PUA  
DAC A power-up. When set, this bit places DAC A in normal operating mode. When cleared, this bit places DAC A in power-down  
mode (default). If the clamp enable bit of the control register is cleared, DAC A powers down automatically upon detection of an  
overcurrent and PUA is cleared to reflect this.  
PUB  
DAC B power-up. When set, this bit places DAC B in normal operating mode. When cleared, this bit places DAC B in power-down  
mode (default). If the clamp enable bit of the control register is cleared, DAC A powers down automatically upon detection of an  
overcurrent and PUA is cleared to reflect this.  
TSD  
OCA  
OCB  
Thermal shutdown alert (read-only bit). In the event of an overtemperature situation, both DACs are powered down and this bit is set.  
DAC A overcurrent alert (read-only bit). In the event of an overcurrent situation on DAC A, this bit is set.  
DAC B overcurrent alert (read-only bit). In the event of an overcurrent situation on DAC B, this bit is set.  
Rev. 0 | Page 26 of 32  
 
 
 
 
 
 
 
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