AD574

更新时间： 2024-01-29 17:26:41

品牌	Logo	应用领域
亚德诺 - ADI		转换器
页数	文件大小	规格书
12页	383K
描述
Complete 12-Bit A/D Converter

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技术参数
数据手册

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AD574 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.56	转换器类型：	ADC, SUCCESSIVE APPROXIMATION
输出位码：	OFFSET BINARY	Base Number Matches：	1

AD574 数据手册

AD574A

GENERAL A/D CONVERTER INTERFACE

CONSIDERATIONS

to valid logic levels after the conversion cycle is completed. The

STS line goes high 600 ns after R/C goes low and returns low

300 ns after data is valid.

A typical A/D converter interface routine involves several

operations. First, a write to the ADC address initiates a conver-

sion. The processor must then wait for the conversion cycle to

complete, since most ADCs take longer than one instruction

cycle to complete a conversion. Valid data can, of course, only

be read after the conversion is complete. The AD574A provides

an output signal (STS) which indicates when a conversion is in

progress. This signal can be polled by the processor by reading

it through an external three-state buffer (or other input port).

The STS signal can also be used to generate an interrupt upon

completion of conversion, if the system timing requirements are

critical (bear in mind that the maximum conversion time of the

AD574A is only 35 microseconds) and the processor has other

tasks to perform during the ADC conversion cycle. Another

possible time-out method is to assume that the ADC will take

35 microseconds to convert, and insert a sufficient number of

“do-nothing” instructions to ensure that 35 microseconds of

processor time is consumed.

If conversion is initiated by a high pulse as shown in Figure 12,

the data lines are enabled during the time when R/C is high.

The falling edge of R/C starts the next conversion, and the data

lines return to three-state (and remain three-state) until the next

high pulse of R/C.

Figure 12. High Pulse for R/C—Outputs Enabled While R/C

High, Otherwise High-Z

Once it is established that the conversion is finished, the data

can be read. In the case of an ADC of 8-bit resolution (or less),

a single data read operation is sufficient. In the case of convert-

ers with more data bits than are available on the bus, a choice of

data formats is required, and multiple read operations are needed.

The AD574A includes internal logic to permit direct interface

to 8-bit or 16-bit data buses, selected by connection of the 12/8

input. In 16-bit bus applications (12/8 high) the data lines

(DB11 through DB0) may be connected to either the 12 most

significant or 12 least significant bits of the data bus. The re-

maining four bits should be masked in software. The interface

to an 8-bit data bus (12/8 low) is done in a left-justified format.

The even address (A0 low) contains the 8 MSBs (DB11 through

DB4). The odd address (A0 high) contains the 4 LSBs (DB3

through DB0) in the upper half of the byte, followed by four

trailing zeroes, thus eliminating bit masking instructions.

Table IV. Stand-Alone Mode Timing

Symbol Parameter

t_HRLLow R/C Pulse Width

Min Typ Max Units

250

t_DS

t_HDR

t_HL

STS Delay from R/C

Data Valid After R/C Low

Output Float Delay

600

150

t_HS

STS Delay After Data Valid 300

1000 ns

t_HRH

t_DDR

High R/C Pulse Width

Data Access Time

300

250

Usually the low pulse for R/C stand-alone mode will be used.

Figure 13 illustrates a typical stand-alone configuration for 8086

type processors. The addition of the 74F/S374 latches improves

bus access/release times and helps minimize digital feedthrough

to the analog portion of the converter.

It is not possible to rearrange the AD574A data lines for right

justified 8-bit bus interface.

Figure 14. AD574A Data Format for 8-Bit Bus

SPECIFIC PROCESSOR INTERFACE EXAMPLES

Z-80 System Interface

The AD574A may be interfaced to the Z-80 processor in an I/O

or memory mapped configuration. Figure 15 illustrates an I/O

or mapped configuration. The Z-80 uses address lines A0–A7 to

decode the I/O port address.

Figure 13. 8086 Stand-Alone Configuration

INTERFACING THE AD574A TO MICROPROCESSORS

The control logic of the AD574A makes direct connection to

most microprocessor system buses possible. While it is impos-

sible to describe the details of the interface connections for every

microprocessor type, several representative examples will be

described here.

An interesting feature of the Z-80 is that during I/O operations a

single wait state is automatically inserted, allowing the AD574A

to be used with Z-80 processors having clock speeds up to 4MHz.

For applications faster than 4 MHz use the wait state generator

in Figure 16. In a memory mapped configuration the AD574A

may be interfaced to Z-80 processors with clock speeds of up to

2.5 MHz.

–10–

REV. B

1...7 8 91011 12

中文翻译

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与AD574相关器件

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AD5744	ADI	获取价格	Complete, Quad, 14/16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC
AD5744ASU	ADI	获取价格	Complete, Quad, 14/16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC
AD5744ASU-REEL7	ADI	获取价格	IC IC,D/A CONVERTER,QUAD,14-BIT,CMOS,TQFP,32PIN, Digital to Analog Converter
AD5744BSU	ADI	获取价格	Complete, Quad, 14/16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC
AD5744BSU-REEL7	ADI	获取价格	IC IC,D/A CONVERTER,QUAD,14-BIT,CMOS,TQFP,32PIN, Digital to Analog Converter
AD5744BSUZ	ADI	获取价格	IC SERIAL INPUT LOADING, 8 us SETTLING TIME, 14-BIT DAC, PQFP32, LEAD FREE, PLASTIC, MS-02
AD5744BSUZ-REEL7	ADI	获取价格	IC SERIAL INPUT LOADING, 8 us SETTLING TIME, 14-BIT DAC, PQFP32, LEAD FREE, PLASTIC, MS-02
AD5744CSU	ADI	获取价格	Complete, Quad, 14/16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC
AD5744CSU-REEL7	ADI	获取价格	IC IC,D/A CONVERTER,QUAD,14-BIT,CMOS,TQFP,32PIN, Digital to Analog Converter
AD5744CSUZ	ADI	获取价格	IC SERIAL INPUT LOADING, 8 us SETTLING TIME, 14-BIT DAC, PQFP32, LEAD FREE, PLASTIC, MS-02

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