AD573JN/+

更新时间： 2024-02-04 07:01:26

品牌	Logo	应用领域
亚德诺 - ADI		转换器
页数	文件大小	规格书
8页	330K
描述
IC IC,A/D CONVERTER,SINGLE,10-BIT,BIPOLAR,DIP,20PIN, Analog to Digital Converter

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AD573JN/+ 技术参数

Source Url Status Check Date：	2013-05-01 14:56:14.576	是否无铅：	含铅
是否Rohs认证：	不符合	生命周期：	Active
零件包装代码：	DIP	包装说明：	DIP, DIP20,.3
针数：	20	Reach Compliance Code：	not_compliant
ECCN代码：	3A001.A.2.C	HTS代码：	8542.39.00.01
风险等级：	7.77	最大模拟输入电压：	5 V
最小模拟输入电压：	-5 V	最长转换时间：	30 µs
转换器类型：	ADC, SUCCESSIVE APPROXIMATION	JESD-30 代码：	R-CDIP-T20
JESD-609代码：	e0	长度：	25.4 mm
最大线性误差 (EL)：	0.0977%	标称负供电电压：	-15 V
模拟输入通道数量：	1	位数：	10
功能数量：	1	端子数量：	20
最高工作温度：	125 °C	最低工作温度：	-55 °C
输出位码：	BINARY, OFFSET BINARY	输出格式：	PARALLEL, WORD
封装主体材料：	CERAMIC, METAL-SEALED COFIRED	封装代码：	DIP
封装等效代码：	DIP20,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5,-12/-15 V	认证状态：	Not Qualified
采样速率：	0.05 MHz	采样并保持/跟踪并保持：	SAMPLE
座面最大高度：	5.08 mm	子类别：	Analog to Digital Converters
标称供电电压：	5 V	表面贴装：	NO
技术：	BIPOLAR	温度等级：	MILITARY
端子面层：	Tin/Lead (Sn63Pb37)	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	7.62 mm
Base Number Matches：	1

AD573JN/+ 数据手册

AD573

It is also possible to write a faster-executing assembly-language

routine to control the AD573. Such a routine will require a de-

lay between starting and reading the converter. This can be eas-

ily implemented by calling the Apple’s WAIT subroutine (which

resides at location $FCA8) after loading the accumulator with a

number greater than or equal to two.

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

20-Pin Ceramic DIP Package (“D”)

8085-Series Microprocessor Interface

The AD573 can also be used with 8085-series microprocessors.

These processors use separate control signals for RD and WR,

as opposed to the single R/W control signal used in the 6800/

6500 series processors.

There are two constraints related to operation of the AD573

with 8085-series processors. The first problem is the width of

the CONVERT pulse. The circuit shown in Figure 17 (essen-

tially the same as that shown in Figure 13) will produce a wide

enough CONVERT pulse when the 8085 is running at 5 MHz.

For 8085 systems running at slower clock rates (3 MHz), the

flip-flop-based circuit can be eliminated since the WR pulse will

be approximately 500 ns wide.

20-Pin Plastic DIP Package (“N”)

The other consideration is the access time of the AD573’s three-

state output data buffers, which is 250 ns maximum. It may be

necessary to insert wait states during RD operations from the

AD573. This will not be a problem in systems using memories

with comparable access times, since wait states will have already

been provided in the basic system design.

P-20A PLCC

Figure 17. AD573–8085A Interface Connections

The following assembly-language subroutine can be used to

control an AD573 residing at memory locations 3000_Hand

3001_H. The 10 bits of data are returned (left-justified) in the

DE register pair.

ADC: LXI H, 3000 ; LOAD HL WITH AD573 ADDRESS

MOV M, A ; START CONVERSION

MVI B, 06

LOOP: DCR B

JNZ LOOP

; LOAD DELAY PERIOD

; DELAY LOOP

;

MOV A, M ; READ LOW BYTE

ANI C0

MOV E, A

INR L

; MASK LOWER 6 BITS

; STORE CLEAN LOW BYTE IN E

; LOAD HIGH BYTE ADDRESS

MOV D, M ; MOVE HIGH BYTE TO D

RET ; EXIT

–8–

REV. A

1...5 6 78

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