AD573JN/+

更新时间： 2024-02-09 19:00:42

品牌	Logo	应用领域
亚德诺 - ADI		转换器
页数	文件大小	规格书
8页	330K
描述
IC IC,A/D CONVERTER,SINGLE,10-BIT,BIPOLAR,DIP,20PIN, Analog to Digital Converter

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AD573JN/+ 技术参数

Source Url Status Check Date：	2013-05-01 14:56:14.576	是否无铅：	含铅
是否Rohs认证：	不符合	生命周期：	Active
零件包装代码：	DIP	包装说明：	DIP, DIP20,.3
针数：	20	Reach Compliance Code：	not_compliant
ECCN代码：	3A001.A.2.C	HTS代码：	8542.39.00.01
风险等级：	7.77	最大模拟输入电压：	5 V
最小模拟输入电压：	-5 V	最长转换时间：	30 µs
转换器类型：	ADC, SUCCESSIVE APPROXIMATION	JESD-30 代码：	R-CDIP-T20
JESD-609代码：	e0	长度：	25.4 mm
最大线性误差 (EL)：	0.0977%	标称负供电电压：	-15 V
模拟输入通道数量：	1	位数：	10
功能数量：	1	端子数量：	20
最高工作温度：	125 °C	最低工作温度：	-55 °C
输出位码：	BINARY, OFFSET BINARY	输出格式：	PARALLEL, WORD
封装主体材料：	CERAMIC, METAL-SEALED COFIRED	封装代码：	DIP
封装等效代码：	DIP20,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5,-12/-15 V	认证状态：	Not Qualified
采样速率：	0.05 MHz	采样并保持/跟踪并保持：	SAMPLE
座面最大高度：	5.08 mm	子类别：	Analog to Digital Converters
标称供电电压：	5 V	表面贴装：	NO
技术：	BIPOLAR	温度等级：	MILITARY
端子面层：	Tin/Lead (Sn63Pb37)	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	7.62 mm
Base Number Matches：	1

AD573JN/+ 数据手册

AD573

CONTROL AND TIMING OF THE AD573

The operation of the AD573 is controlled by three inputs:

CONVERT, HBE and LBE.

pulse, and gating it with RD to enable the output buffers. The

use of a memory address and memory WR and RD signals de-

notes “memory-mapped” I/O interfacing, while the use of a

separate I/O address space denotes “isolated I/O” interfacing. In

8-bit bus systems, the 10-bit AD573 will occupy two locations

when data is to be read; therefore, two (usually consecutive) ad-

dresses must be decoded. One of the addresses can also be used

as the address which produces the CONVERT signal during

WR operations.

Starting a Conversion

The conversion cycle is initiated by a positive going CONVERT

pulse at least 500 ns wide. The rising edge of this pulse resets

the internal logic, clears the result of the previous conversion,

and sets DR high. The falling edge of CONVERT begins the

conversion cycle. When conversion is completed DR returns

low. During the conversion cycle, HBE and LBE should be held

high. If HBE or LBE goes low during a conversion, the data

output buffers will be enabled and intermediate conversion re-

sults will be present on the data output pins. This may cause

bus conflicts if other devices in a system are trying to use the bus.

Figure 11 shows a generalized diagram of the control logic for

an AD573 interfaced to an 8-bit data bus, where two addresses

(ADC ADDR and ADC ADDR + 1) have been decoded. ADC

ADDR starts the converter when written to (the actual data be-

ing written to the converter does not matter) and contains the

high byte data during read operations. ADC ADDR + 1 per-

forms no function during write operations, but contains the low

byte data during read operations.

+ V

t_C

CONVERT

t_CS

t_DSC

+ V

Figure 9. Convert Timing

Reading the Data

The three-state data output buffers are enabled by HBE and

LBE. Access time of these buffers is typically 150 ns (250 maxi-

mum). The data outputs remain valid until 50 ns after the en-

able signal returns high, and are completely into the high

impedance state 100 ns later.

+ V

LBE OR HBE

Figure 11. General AD573 Interface to 8-Bit Microprocessor

t_DD

t_HD

HIGH

IMPEDANCE

HIGH

IMPEDANCE

In systems where this read-write interface is used, at least 30

microseconds (the maximum conversion time) must be allowed

to pass between starting a conversion and reading the results.

This delay or “timeout” period can be implemented in a short

software routine such as a countdown loop, enough dummy in-

structions to consume 30 microseconds, or enough actual useful

instructions to consume the required time. In tightly-timed sys-

tems, the DR line may be read through an external three-state

buffer to determine precisely when a conversion is complete.

Higher speed systems may choose to use DR to signal an inter-

rupt to the processor at the end of a conversion.

DB0–DB7

DB8–DB9

DATA

VALID

t_HL

Figure 10. Read Timing

TIMING SPECIFICATIONS (All grades, T_A= T_MIN–T_MAX

)

Parameter

Symbol Min Typ Max Units

CONVERT Pulse Width

t_CS

500

–

10 20

–

1.5 µs

30 µs

150 250 ns

DR Delay from CONVERT t_DSC

Conversion Time

Data Access Time

Data Valid after HBE/LBE

High

t_C

t_DD

t_HD

t_HL

–

Output Float Delay

100 200 ns

MICROPROCESSOR INTERFACE CONSIDERATIONS—

GENERAL

When an analog-to-digital converter like the AD573 is inter-

faced to a microprocessor, several details of the interface must

be considered. First, a signal to start the converter must be gen-

erated; then an appropriate delay period must be allowed to pass

before valid conversion data may be read. In most applications,

the AD573 can interface to a microprocessor system with little

or no external logic.

The most popular control signal configuration consists of de-

coding the address assigned to the AD573, then gating this sig-

nal with the system’s WR signal to generate the CONVERT

Figure 12. Typical AD573 Interface Timing Diagram

REV. A

–6–

1...3 4 567 8

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