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AD573JN/+ PDF预览

AD573JN/+

更新时间: 2024-01-11 03:02:09
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
8页 330K
描述
IC IC,A/D CONVERTER,SINGLE,10-BIT,BIPOLAR,DIP,20PIN, Analog to Digital Converter

AD573JN/+ 技术参数

Source Url Status Check Date:2013-05-01 14:56:14.576是否无铅: 含铅
是否Rohs认证: 不符合生命周期:Active
零件包装代码:DIP包装说明:DIP, DIP20,.3
针数:20Reach Compliance Code:not_compliant
ECCN代码:3A001.A.2.CHTS代码:8542.39.00.01
风险等级:7.77最大模拟输入电压:5 V
最小模拟输入电压:-5 V最长转换时间:30 µs
转换器类型:ADC, SUCCESSIVE APPROXIMATIONJESD-30 代码:R-CDIP-T20
JESD-609代码:e0长度:25.4 mm
最大线性误差 (EL):0.0977%标称负供电电压:-15 V
模拟输入通道数量:1位数:10
功能数量:1端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出位码:BINARY, OFFSET BINARY输出格式:PARALLEL, WORD
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:DIP
封装等效代码:DIP20,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5,-12/-15 V认证状态:Not Qualified
采样速率:0.05 MHz采样并保持/跟踪并保持:SAMPLE
座面最大高度:5.08 mm子类别:Analog to Digital Converters
标称供电电压:5 V表面贴装:NO
技术:BIPOLAR温度等级:MILITARY
端子面层:Tin/Lead (Sn63Pb37)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

AD573JN/+ 数据手册

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AD573  
ABSOLUTE MAXIMUM RATINGS  
V+ to Digital Common . . . . . . . . . . . . . . . . . . . . . 0 V to +7 V  
V– to Digital Common . . . . . . . . . . . . . . . . . . . 0 V to –16.5 V  
Analog Common to Digital Common . . . . . . . . . . . . . . . ±1 V  
Analog Input to Analog Common . . . . . . . . . . . . . . . . . ±15 V  
Control Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to V+  
Digital Outputs (High Impedance State) . . . . . . . . . . 0 V to V+  
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 mW  
ORDERING GUIDE1  
Temperature  
Range  
Relative  
Accuracy  
Model  
Package Option2  
AD573JN  
AD573KN  
AD573JP  
AD573KP  
AD573JD  
AD573KD  
AD573 SD  
20-Pin Plastic DIP (N-20)  
20-Pin Plastic DIP (N-20)  
0°C to +70°C  
0°C to +70°C  
0°C to +70°C  
0°C to +70°C  
0°C to +70°C  
0°C to +70°C  
–55°C to +125°C  
±1 LSB max  
±1/2 LSB max  
±1 LSB max  
±1/2 LSB max  
±1 LSB max  
±1/2 LSB max  
±1 LSB max  
20-Pin Leaded Chip Carrier (P-20A)  
20-Pin Leaded Chip Carrier (P-20A)  
20-Pin Ceramic DIP (D-20)  
20-Pin Ceramic DIP (D-20)  
20-Pin Ceramic DIP (D-20)  
NOTES  
1For details on grade and package offerings screened in accordance with MIL-STD-883, refer to Analog Devices Military  
Products Databook.  
2D = Ceramic DIP; N = Plastic DIP; P = Plastic Leaded Chip Carrier.  
DIGITAL  
COMMON  
FUNCTIONAL DESCRIPTION  
V+  
5k  
V–  
CONVERT  
A block diagram of the AD573 is shown in Figure 1. The posi-  
tive CONVERT pulse must be at least 500 ns wide. DR goes  
high within 1.5 µs after the leading edge of the convert pulse  
indicating that the internal logic has been reset. The negative  
edge of the CONVERT pulse initiates the conversion. The in-  
ternal 10-bit current output DAC is sequenced by the integrated  
injection logic (I2L) successive approximation register (SAR)  
from its most significant bit to least significant bit to provide an  
output current which accurately balances the input signal cur-  
rent through the 5 kresistor. The comparator determines  
whether the addition of each successively weighted bit current  
causes the DAC current sum to be greater or less than the input  
current; if the sum is more, the bit is turned off. After testing all  
bits, the SAR contains a 10-bit binary code which accurately  
represents the input signal to within 1/2 LSB (0.05% of full scale).  
MSB  
DB9  
ANALOG  
IN  
DB8  
DB7  
DB6  
ANALOG  
COMMON  
10-BIT  
10-BIT  
SAR  
CURRENT  
OUTPUT  
DAC  
HIGH  
BYTE  
DB5  
DB4  
DB3  
DB2  
COMP-  
ARATOR  
INT  
CLOCK  
BIPOLAR  
OFFSET  
CONTROL  
DB1  
DB0  
LOW  
BYTE  
LSB  
HBE  
LBE  
BURIED ZENER REF  
DATA  
READY  
AD573  
The SAR drives DR low to indicate that the conversion is com-  
plete and that the data is available to the output buffers. HBE  
and LBE can then be activated to enable the upper 8-bit and  
lower 2-bit buffers as desired. HBE and LBE should be brought  
high prior to the next conversion to place the output buffers in  
the high impedance state.  
Figure 1. Functional Block Diagram  
UNIPOLAR CONNECTION  
The AD573 contains all the active components required to per-  
form a complete A/D conversion. Thus, for many applications,  
all that is necessary is connection of the power supplies (+5 V  
and –12 V to –15 V), the analog input and the convert pulse.  
However, there are some features and special connections which  
should be considered for achieving optimum performance. The  
functional pinout is shown in Figure 2.  
The temperature compensated buried Zener reference provides  
the primary voltage reference to the DAC and ensures excellent  
stability with both time and temperature. The bipolar offset in-  
put controls a switch which allows the positive bipolar offset  
current (exactly equal to the value of the MSB less 1/2 LSB) to  
be injected into the summing (+) node of the comparator to  
offset the DAC output. Thus the nominal 0 V to +10 V unipolar  
input range becomes a –5 V to +5 V range. The 5 kthin-film  
input resistor is trimmed so that with a full-scale input signal, an  
input current will be generated which exactly matches the DAC  
output with all bits on.  
The standard unipolar 0 V to +10 V range is obtained by short-  
ing the bipolar offset control pin (Pin 16) to digital common  
(Pin 17).  
REV. A  
–3–  

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