AD5737X

更新时间： 2024-01-11 10:42:14

品牌	Logo	应用领域
亚德诺 - ADI		转换器数模转换器功率控制
页数	文件大小	规格书
31页	640K
描述
Quad Channel, 16-Bit, Serial Input, 4-20mA Output DAC, Dynamic Power Control, HART Connectivity

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技术参数
数据手册

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AD5737X 技术参数

生命周期：	Obsolete	零件包装代码：	QFN
包装说明：	,	针数：	64
Reach Compliance Code：	unknown	风险等级：	5.77
Is Samacsys：	N	转换器类型：	D/A CONVERTER
JESD-30 代码：	S-XQCC-N64	位数：	16
端子数量：	64	封装主体材料：	UNSPECIFIED
封装形状：	SQUARE	封装形式：	CHIP CARRIER
认证状态：	Not Qualified	表面贴装：	YES
端子形式：	NO LEAD	端子位置：	QUAD
Base Number Matches：	1

AD5737X 数据手册

Preliminary Technical Data

ABSOLUTE MAXIMUM RATINGS

AD5757/AD5737

T_A= 25°C, unless otherwise noted. Transient currents of up to

100 mA do not cause SCR latch-up.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 5.

Parameter

Rating

AV_DDto AGND, DGND

AV_SSto AGND, DGND

AV_DDto AV_SS

AV_ccto AGND

DVDD to DGND

Digital Inputs to DGND

−0.3 V to +33 V

+0.3 V to −28 V

−0.3 V to +60 V

−0.3 V to +7 V

ESD CAUTION

−0.3 V to DVDD + 0.3 V or

+7 V (whichever is less)

Digital Outputs to DGND

REFIN/REFOUT to AGND

−0.3 V to DVDD + 0.3 V

−0.3 V to AVDD + 0.3 V or +7

V (whichever is less)

I_OUTA,B,C,D to AGND

R_SETA,B,C,Dto AGND

−0.3 V to AV_DD

−0.3 V to AVDD + 0.3 V or +7

V (whichever is less)

SW_A,B,C,D/ V_BOOSTA,B,C,Dto AGND

−0.3 to +33 V

COMP_{DCDC_A,B,C,D}/ CHART_A,B,C,Dto AGND −0.3 V to +5 V

AGND, GNDSW_A,B,C,Dto DGND

Operating Temperature Range (T_A)

Industrial¹

Storage Temperature Range

Junction Temperature (T_Jmax)

64-Lead LFCSP

θ_JAThermal Impedance²

Power Dissipation

−0.3 V to +0.3 V

−40°C to +105°C

−65°C to +150°C

125°C

20°C/W

(T_Jmax – T_A)/θ_JA

JEDEC Industry Standard

J-STD-020

Lead Temperature

Soldering

¹Power dissipated on chip must be derated to keep the junction temperature

below 125°C

²Based on a JEDEC 4 layer test board

Rev. PrD | Page 9 of 31

1...6 7 8910 11 12...31

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